arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP

In the Arm ISA there are some sys reg numbers which are reserved for
implementation defined registers. The default behaviour is to to treat
them as unimplemented registers. It is now possible to change this
behaviour at runtime and treat them as NOP. In this way an access to
those register won't make simulation fail.

Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10504
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Fix mrc,mcr to cop14 disassemble

This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions.

Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9681
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: IMPLEMENTATION DEFINED register

A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.

Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions

This patch adds support for the ARMv7 cache maintenance
intructions:
* mcr dccmvac cleans a VA to the PoC
* mcr dcimvac invalidates a VA to the PoC
* mcr dccimvac cleans and invalidates a VA to the PoC
* mcr dccmvau cleans a VA to the PoU

Change-Id: I6511f203039ca145cc9128ddf61d09d6d7e40c10
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5059
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: change instruction classes to catch hyp traps

Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7

arm: Mark some miscregs (timer counter) registers at unverifiable.

The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.

arm: More UBSan cleanups after additional full-system runs

Some incorrect casting to IntRegIndex, and a few uninitialized members
in the i8254xGBe device.

arm: Fixed undefined behaviours identified by gcc

This patch fixes the runtime errors highlighted by the undefined
behaviour sanitizer. In the end there were two issues. First, when
rotating an immediate, we ended up shifting an uint32_t by 32 in some
cases. This case is fixed by checking for a rotation by 0
positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and
a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex
as an IntRegIndex. This issue is resolved by introducing a
MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types.

With these fixes there are no runtime errors identified for the full
ARM regressions.

arm: Don't use a stack allocated mnemonic

FailUnimplemented passed a stack created mnemonic as a const char * which
causes some grief when the stack goes away.

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

scons: Add warning for missing declarations

This patch enables warnings for missing declarations. To avoid issues
with SWIG-generated code, the warning is only applied to non-SWIG
code.

ARM: Add limited CP14 support.

New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.

CP15 c15: enable execution with accesses to c15 registers

Previously, coprocessor accesses to CP15 c15 would fault. This patch
enables accesses but prints out a warning, as the registers are not implemented.

ARM: Do something for ISB, DSB, DMB

ARM: Adds dummy support for a L2 latency miscreg.

ARM: The ARM decoder should not panic when decoding undefined holes is arch.

This can abort simulations when the fetch unit runs ahead and speculatively
decodes instructions that are off the execution path.

ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.

Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.

ARM: Adding a bogus fault that does nothing.
This fault can used to flush the pipe, not including the faulting instruction.

The particular case I needed this was for a self-modifying code. It needed to
drain the store queue and force the following instruction to refetch from
icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.

ARM: Implement some more misc registers

ARM: Implement a version of mcr and mrc that works in user mode.

ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.

ARM: Ignore reads and writes to DCIMVAC.

ARM: Move the CP15 decode block into a function.

ARM: Warn/ignore when TLB maintenance operations are performed.

ARM: Convert the CP15 registers from MPU to MMU.

ARM: Ignore/warn on accesses to the DRBAR, DRACR, and DRSR registers.

ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.

ARM: Ignore/warn access to the bpimva registers.

ARM: Ignore/warn on accesses to the dccmvac register.

ARM: Ignore/warn on accesses to icimvau.

ARM: Ignore/warn on ICIALLUIS.

ARM: Decode the unimplemented data barrier CP15 accesses.

These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).

ARM: Decode the unimplemented cp15 instruction barrier.

ARM: Ignore accesses to DCCIMVAC.

ARM: Warn about and ignore accesses to DCCISW.

This register is supposed to "Clean and invalidate data or unified cache line
by set/way." Since there isn't a good way to do that, we'll just ignore these
and warn about it.

ARM: Decode the thumb versions of the mcr and mrc instructions.

ARM: Replace the versions of MRS and MSR in the ARM decoder with the new ones.

ARM: Implement SVC (was SWI) outside of the decoder.