style: [patch 1/22] use /r/3648/ to reorganize includes

x86: revamp cmpxchg8b/cmpxchg16b implementation

The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models. It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops. It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.

This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg. This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.

includes: sort all includes

copyright: Change HP copyright on x86 code to be more friendly

X86: Move the function that prints memory args into the inst base class.

X86: Hide the irrelevant portions of the address components for load and store microops.

X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".

Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.

Pull some hard coded base classes out of the isa description.