Searched hist:2007 (Results 751 - 775 of 895) sorted by relevance

<<313233343536

/gem5/src/base/loader/
H A Draw_object.cc3904:88a6585546e1 Tue Jan 16 19:09:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Don't add symbols for loaded files to symbol table since they are pretty much meaningless with all the copying that goes on
/gem5/src/sim/
H A Ddebug.cc4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
H A Dstat_control.hh4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and
expose all of the relevant functionality to python. Clean
up the mysql code while we're at it.
H A Deventq.cc4212:0d50e6c98d13 Mon Mar 12 17:23:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault
4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
4017:6bbb3b9b0e88 Tue Feb 06 13:04:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix for previous commit: need to ifdef NDEBUG on the
definition as well as the declaration.
4016:1d09f041eefa Tue Feb 06 01:05:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Use an instance counter to give Events repeatable IDs
in debugging mode (especially valuable for tracediff).
H A Darguments.hh4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
H A Dprocess_impl.hh4434:2ea7b6e0b78f Wed May 09 15:37:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fix the translating ports so it can add a page on a fault
/gem5/tests/configs/
H A Dtsunami-simple-timing-dual.py4966:427e4677e589 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Regression: Add an I/O Cache to the full system regressions that have a cache.
4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object.
4444:0648bdc8d1c9 Thu May 10 18:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs
4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are
directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
H A Dmemtest.py4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object.
4467:cb5715e021ca Sat May 19 00:24:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.
4444:0648bdc8d1c9 Thu May 10 18:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs
4019:cdfb21ba304e Wed Feb 07 00:16:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Add short memtest run to quick regressions.
Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
/gem5/src/cpu/o3/
H A Dscoreboard.cc4642:d7b2de2d72f1 Sun Apr 22 13:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the floating point zero register special handling only apply for ALPHA.
H A DO3CPU.py5236:0050ad4fb3ef Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement a page table walker.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4597:063f25d13229 Wed Jun 20 11:14:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Make sure all parameters have default values if they're
supposed to and make sure parameters have the right type.
Also make sure that any object that should be an intermediate
type has the right options set.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
H A Dcommit_impl.hh5108:3b59ba14a7f3 Tue Oct 02 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> CPU: Make the cpus check the pc event queues in SE mode.
5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks()
4873:b135f6e6adfe Sat Jun 30 20:45:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Event descriptions should not end in "event"
(they function as adjectives not nouns)
4650:bb9977571ff4 Wed May 09 23:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro
4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
4632:be5b8f67b8fb Fri Apr 13 09:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remove most of the special handling for delay slots since they have to be squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
4405:57af43e114b5 Thu Apr 26 00:02:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Remove unnecessary check.
4329:52057dbec096 Wed Apr 04 15:38:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
4318:eb4241362a80 Mon Apr 02 13:55:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Remove/comment out DPRINTFs that were causing a segfault.

The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
4288:1fc3aa7ad095 Sun Mar 25 00:47:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update for new trace data behavior.
H A Dthread_context.hh5259:74ef5093154f Thu Nov 15 19:48:00 EST 2007 Korey Sewell <ksewell@umich.edu> add microPC stuff back in. got deleted on changeset propragation somehow.
5250:42577371ff31 Thu Nov 15 03:10:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
5249:49d44a466496 Thu Nov 15 00:14:00 EST 2007 Korey Sewell <ksewell@umich.edu> branch merge
5235:f07f46843886 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the micropc available through the thread context objects.
This is necssary for fault handlers that branch to non-zero micro PCs.
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
/gem5/src/arch/x86/
H A Dremote_gdb.cc4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files.
H A Dinterrupts.hh5134:1cdc6876bc9e Sun Oct 07 21:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the Interrupts class complain less.
5133:a88763dd4a84 Sun Oct 07 20:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Adjust the config scripts for x86 fs.
5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile.
4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86.
/gem5/src/dev/mips/
H A Dmalta_cchip.cc5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dmalta_io.cc5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dmalta.cc5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/alpha/linux/
H A Dlinux.hh4131:660ebc4994a9 Sun Mar 04 22:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Don't use the exact same name as a system header #define
/gem5/src/arch/alpha/
H A DAlphaSystem.py4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
/gem5/src/arch/mips/
H A DMipsSystem.py5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/sparc/linux/
H A Dlinux.hh4188:6a9ac3b35285 Fri Mar 09 17:14:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Split the syscall table, SPARC specific syscall implementations, and the 32 bit syscall table into it's own file. Corrected problems with the stat structure. These should be tested on 64 bit x86 and SPARC machines.
/gem5/src/cpu/
H A Dop_class.hh4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
H A DSConscript5217:bb810bb8ca2d Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Add function to explictly compare thread contexts after copying.
5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
/gem5/src/dev/alpha/
H A DTsunami.py4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
/gem5/src/base/stats/
H A Doutput.hh4085:4df21265d806 Wed Feb 21 13:15:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Fix majory brokenness in my previous MySQL commit, basically
this is just a shuffling around of code and fixes to make
stuff commit properly

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