1/*
2 * Copyright (c) 2010, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 */
42
43#ifndef __CPU__OP_CLASS_HH__
44#define __CPU__OP_CLASS_HH__
45
46#include "enums/OpClass.hh"
47
48/*
49 * Do a bunch of wonky stuff to maintain backward compatability so I
50 * don't have to change code in a zillion places.
51 */
52using Enums::OpClass;
53using Enums::No_OpClass;
54
55static const OpClass IntAluOp = Enums::IntAlu;
56static const OpClass IntMultOp = Enums::IntMult;
57static const OpClass IntDivOp = Enums::IntDiv;
58static const OpClass FloatAddOp = Enums::FloatAdd;
59static const OpClass FloatCmpOp = Enums::FloatCmp;
60static const OpClass FloatCvtOp = Enums::FloatCvt;
61static const OpClass FloatMultOp = Enums::FloatMult;
62static const OpClass FloatMultAccOp = Enums::FloatMultAcc;
63static const OpClass FloatDivOp = Enums::FloatDiv;
64static const OpClass FloatMiscOp = Enums::FloatMisc;
65static const OpClass FloatSqrtOp = Enums::FloatSqrt;
66static const OpClass SimdAddOp = Enums::SimdAdd;
67static const OpClass SimdAddAccOp = Enums::SimdAddAcc;
68static const OpClass SimdAluOp = Enums::SimdAlu;
69static const OpClass SimdCmpOp = Enums::SimdCmp;
70static const OpClass SimdCvtOp = Enums::SimdCvt;
71static const OpClass SimdMiscOp = Enums::SimdMisc;
72static const OpClass SimdMultOp = Enums::SimdMult;
73static const OpClass SimdMultAccOp = Enums::SimdMultAcc;
74static const OpClass SimdShiftOp = Enums::SimdShift;
75static const OpClass SimdShiftAccOp = Enums::SimdShiftAcc;
76static const OpClass SimdDivOp = Enums::SimdDiv;
77static const OpClass SimdSqrtOp = Enums::SimdSqrt;
78static const OpClass SimdReduceAddOp = Enums::SimdReduceAdd;
79static const OpClass SimdReduceAluOp = Enums::SimdReduceAlu;
80static const OpClass SimdReduceCmpOp = Enums::SimdReduceCmp;
81static const OpClass SimdFloatAddOp = Enums::SimdFloatAdd;
82static const OpClass SimdFloatAluOp = Enums::SimdFloatAlu;
83static const OpClass SimdFloatCmpOp = Enums::SimdFloatCmp;
84static const OpClass SimdFloatCvtOp = Enums::SimdFloatCvt;
85static const OpClass SimdFloatDivOp = Enums::SimdFloatDiv;
86static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc;
87static const OpClass SimdFloatMultOp = Enums::SimdFloatMult;
88static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
89static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
90static const OpClass SimdFloatReduceCmpOp = Enums::SimdFloatReduceCmp;
91static const OpClass SimdFloatReduceAddOp = Enums::SimdFloatReduceAdd;
92static const OpClass SimdAesOp = Enums::SimdAes;
93static const OpClass SimdAesMixOp = Enums::SimdAesMix;
94static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash;
95static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2;
96static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash;
97static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2;
98static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2;
99static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3;
100static const OpClass SimdPredAluOp = Enums::SimdPredAlu;
101static const OpClass MemReadOp = Enums::MemRead;
102static const OpClass MemWriteOp = Enums::MemWrite;
103static const OpClass FloatMemReadOp = Enums::FloatMemRead;
104static const OpClass FloatMemWriteOp = Enums::FloatMemWrite;
105static const OpClass IprAccessOp = Enums::IprAccess;
106static const OpClass InstPrefetchOp = Enums::InstPrefetch;
107static const OpClass Num_OpClasses = Enums::Num_OpClass;
108
109#endif // __CPU__OP_CLASS_HH__
110