15222Sksewell@umich.edu/* 25222Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35222Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55222Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65222Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75222Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95222Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105222Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115222Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125222Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135222Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145222Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175222Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195222Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205222Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215222Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225222Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235222Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245222Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255222Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265222Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Ali Saidi 295222Sksewell@umich.edu * Rick Strong 305222Sksewell@umich.edu */ 315222Sksewell@umich.edu 325222Sksewell@umich.edu/** @file 335222Sksewell@umich.edu * Emulation of the Malta CChip CSRs 345222Sksewell@umich.edu */ 355222Sksewell@umich.edu 3611793Sbrandon.potter@amd.com#include "dev/mips/malta_cchip.hh" 3711793Sbrandon.potter@amd.com 385222Sksewell@umich.edu#include <deque> 395222Sksewell@umich.edu#include <string> 405222Sksewell@umich.edu#include <vector> 415222Sksewell@umich.edu 425222Sksewell@umich.edu#include "base/trace.hh" 435222Sksewell@umich.edu#include "cpu/intr_control.hh" 445222Sksewell@umich.edu#include "cpu/thread_context.hh" 458739Sgblack@eecs.umich.edu#include "debug/Malta.hh" 465222Sksewell@umich.edu#include "dev/mips/malta.hh" 475222Sksewell@umich.edu#include "dev/mips/maltareg.h" 485222Sksewell@umich.edu#include "mem/packet.hh" 495222Sksewell@umich.edu#include "mem/packet_access.hh" 505222Sksewell@umich.edu#include "mem/port.hh" 515222Sksewell@umich.edu#include "params/MaltaCChip.hh" 525222Sksewell@umich.edu#include "sim/system.hh" 535222Sksewell@umich.edu 545222Sksewell@umich.eduusing namespace std; 555222Sksewell@umich.edu 565222Sksewell@umich.eduMaltaCChip::MaltaCChip(Params *p) 579808Sstever@gmail.com : BasicPioDevice(p, 0xfffffff), malta(p->malta) 585222Sksewell@umich.edu{ 596658Snate@binkert.org warn("MaltaCCHIP::MaltaCChip() not implemented."); 605222Sksewell@umich.edu 615222Sksewell@umich.edu //Put back pointer in malta 625222Sksewell@umich.edu malta->cchip = this; 635222Sksewell@umich.edu 645222Sksewell@umich.edu} 655222Sksewell@umich.edu 665222Sksewell@umich.eduTick 675222Sksewell@umich.eduMaltaCChip::read(PacketPtr pkt) 685222Sksewell@umich.edu{ 6912623Sgabeblack@google.com panic("MaltaCCHIP::read() not implemented."); 705222Sksewell@umich.edu return pioDelay; 715222Sksewell@umich.edu} 725222Sksewell@umich.edu 735222Sksewell@umich.eduTick 745222Sksewell@umich.eduMaltaCChip::write(PacketPtr pkt) 755222Sksewell@umich.edu{ 7612623Sgabeblack@google.com panic("MaltaCCHIP::write() not implemented."); 775222Sksewell@umich.edu return pioDelay; 785222Sksewell@umich.edu} 795222Sksewell@umich.edu 805222Sksewell@umich.eduvoid 815222Sksewell@umich.eduMaltaCChip::clearIPI(uint64_t ipintr) 825222Sksewell@umich.edu{ 8312623Sgabeblack@google.com panic("MaltaCCHIP::clear() not implemented."); 845222Sksewell@umich.edu} 855222Sksewell@umich.edu 865222Sksewell@umich.eduvoid 875222Sksewell@umich.eduMaltaCChip::clearITI(uint64_t itintr) 885222Sksewell@umich.edu{ 8912623Sgabeblack@google.com panic("MaltaCCHIP::clearITI() not implemented."); 905222Sksewell@umich.edu} 915222Sksewell@umich.edu 925222Sksewell@umich.eduvoid 935222Sksewell@umich.eduMaltaCChip::reqIPI(uint64_t ipreq) 945222Sksewell@umich.edu{ 9512623Sgabeblack@google.com panic("MaltaCCHIP::reqIPI() not implemented."); 965222Sksewell@umich.edu} 975222Sksewell@umich.edu 985222Sksewell@umich.edu 995222Sksewell@umich.eduvoid 1005222Sksewell@umich.eduMaltaCChip::postRTC() 1015222Sksewell@umich.edu{ 10212623Sgabeblack@google.com panic("MaltaCCHIP::postRTC() not implemented."); 1035222Sksewell@umich.edu} 1045222Sksewell@umich.edu 1055222Sksewell@umich.eduvoid 1065222Sksewell@umich.eduMaltaCChip::postIntr(uint32_t interrupt) 1075222Sksewell@umich.edu{ 1085222Sksewell@umich.edu uint64_t size = sys->threadContexts.size(); 1095222Sksewell@umich.edu assert(size <= Malta::Max_CPUs); 1105222Sksewell@umich.edu 11111321Ssteve.reinhardt@amd.com for (int i=0; i < size; i++) { 11212623Sgabeblack@google.com //Note: Malta does not use index, but this was added to use the 11312623Sgabeblack@google.com //pre-existing implementation 11412623Sgabeblack@google.com malta->intrctrl->post(i, interrupt, 0); 11512623Sgabeblack@google.com DPRINTF(Malta, "posting interrupt to cpu %d, interrupt %d\n", 11612623Sgabeblack@google.com i, interrupt); 1175222Sksewell@umich.edu } 1185222Sksewell@umich.edu} 1195222Sksewell@umich.edu 1205222Sksewell@umich.eduvoid 1215222Sksewell@umich.eduMaltaCChip::clearIntr(uint32_t interrupt) 1225222Sksewell@umich.edu{ 1235222Sksewell@umich.edu uint64_t size = sys->threadContexts.size(); 1245222Sksewell@umich.edu assert(size <= Malta::Max_CPUs); 1255222Sksewell@umich.edu 12611321Ssteve.reinhardt@amd.com for (int i=0; i < size; i++) { 12712623Sgabeblack@google.com //Note: Malta does not use index, but this was added to use the 12812623Sgabeblack@google.com //pre-existing implementation 12912623Sgabeblack@google.com malta->intrctrl->clear(i, interrupt, 0); 13012623Sgabeblack@google.com DPRINTF(Malta, "clearing interrupt to cpu %d, interrupt %d\n", 13112623Sgabeblack@google.com i, interrupt); 1325222Sksewell@umich.edu } 1335222Sksewell@umich.edu} 1345222Sksewell@umich.edu 1355222Sksewell@umich.edu 1365222Sksewell@umich.eduvoid 13710905Sandreas.sandberg@arm.comMaltaCChip::serialize(CheckpointOut &cp) const 1385222Sksewell@umich.edu{ 1395222Sksewell@umich.edu} 1405222Sksewell@umich.edu 1415222Sksewell@umich.eduvoid 14210905Sandreas.sandberg@arm.comMaltaCChip::unserialize(CheckpointIn &cp) 1435222Sksewell@umich.edu{ 1445222Sksewell@umich.edu} 1455222Sksewell@umich.edu 1465222Sksewell@umich.eduMaltaCChip * 1475222Sksewell@umich.eduMaltaCChipParams::create() 1485222Sksewell@umich.edu{ 1495222Sksewell@umich.edu return new MaltaCChip(this); 1505222Sksewell@umich.edu} 1515222Sksewell@umich.edu 152