Searched hist:2007 (Results 701 - 725 of 895) sorted by relevance
/gem5/src/cpu/ | ||
H A D | BaseCPU.py | 5281:61e396061986 Wed Nov 21 03:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> imported patch pagewalker.patch 5249:49d44a466496 Thu Nov 15 00:14:00 EST 2007 Korey Sewell <ksewell@umich.edu> branch merge 5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh. 5237:6c819dbe8045 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the page table walker, TLB, and related faults. 5236:0050ad4fb3ef Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement a page table walker. 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4968:f1c856d8c460 Wed Aug 08 18:43:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Added fastmem option. Lets CPU accesses to physical memory bypass Bus. 4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. 4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. |
H A D | base.cc | 5311:9ed42a2315ae Tue Dec 18 01:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 5217:bb810bb8ca2d Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Add function to explictly compare thread contexts after copying. 5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks() 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4947:6052dece6776 Sat Aug 04 19:11:00 EDT 2007 Nathan Binkert <nate@binkert.org> switching: turn on profiling after a switch if there's an event 4928:951bd17db218 Sun Jul 29 16:25:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Merge Gabe's changes from head. 4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch 4873:b135f6e6adfe Sat Jun 30 20:45:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Event descriptions should not end in "event" (they function as adjectives not nouns) 4796:e938afbfc8cd Sun Jul 29 16:22:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> BsaeCPU: Get rid of some bad DPRINTFs. People should never put pointers in DPRINTFs; it messes up tracediffs. Plus these used the FullCPU trace flag, which is not right. 4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects. These need to be refined a little still and given parameters. |
H A D | base_dyn_inst_impl.hh | 4654:225cc048edfa Wed Jun 20 22:46:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix compiler errors. 4653:19f884e6a48b Tue Jun 19 21:54:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge 4636:afc8da9f526e Sat Apr 14 13:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. 4032:8b987a6a2afc Fri Mar 23 11:33:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Two fixes: 1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained. src/cpu/base_dyn_inst.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. Also include some functions to allow certain status bits to be cleared. src/cpu/base_dyn_inst_impl.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. src/cpu/o3/fetch_impl.hh: General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called. src/cpu/o3/lsq_unit.hh: Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system. Also be sure to not store-load forward from an uncacheable store. src/cpu/o3/lsq_unit_impl.hh: Check to make sure load-load ordering was maintained. Also handle requests a little more correctly. |
H A D | static_inst.cc | 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. |
/gem5/configs/common/ | ||
H A D | Simulation.py | 5311:9ed42a2315ae Tue Dec 18 01:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. 5211:f7412cfae319 Sat Nov 03 14:41:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpoint: Use checkpoint_dir, if that is not set use outdir (-d), and if that isn't set use cwd. 5185:d970c1ec39c9 Thu Oct 25 22:20:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpoints: Change Simulation.py to not go crazy if the simulation ends before the number of checkpoints requested are created. 5073:1916291dcfda Wed Sep 12 15:27:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Fix directory regex 5072:ff0e3c84a1de Wed Sep 12 15:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Force drain/resume when switching a CPU 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. 3999:ba54519a7a92 Tue Jan 30 18:21:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> fix some checkpointing annoyances -m works as you think it should Ctrl-C actually ends the simulation now |
H A D | FSConfig.py | 5299:e61b9f2a9732 Sun Dec 02 02:09:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move startup code to the system object to initialize a Linux system. 5266:cd03d3753a8d Fri Nov 16 19:37:00 EST 2007 Korey Sewell <ksewell@umich.edu> Accidently kept hardcoded memory value in merge. Remove that and now ALPHA_FS quick regressions pass 5263:e059fb430ef3 Fri Nov 16 19:15:00 EST 2007 Korey Sewell <ksewell@umich.edu> compile-time fix for setMipsOptions function 5253:0ecd2477b9f3 Thu Nov 15 14:20:00 EST 2007 Korey Sewell <ksewell@umich.edu> add setMipsOptions function for MIPS usage 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 5133:a88763dd4a84 Sun Oct 07 20:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Adjust the config scripts for x86 fs. 4982:723f5ce7f7b0 Thu Aug 16 16:49:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> PCI: Move PCI Configuration data into devices now that we can inherit parameters. 4981:33fabf3473a5 Thu Aug 16 16:49:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Devices: Make EtherInts connect in the same way memory ports currently do. 4972:ee5b7df7f436 Sun Aug 12 19:44:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Regression: fix configuration for SPARC_FS 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. |
/gem5/src/dev/ | ||
H A D | io_device.hh | 4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4475:fb185cc1c845 Tue May 22 02:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Change getDeviceAddressRanges to use bool for snoop arg. 4435:7da241055348 Wed May 09 18:20:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add a backoff algorithm when nacks are received by devices add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list 4263:1cd4e07ab60b Thu Mar 22 18:39:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> finish up the coding of the Intel Gb NIC... Many Many bugs to squash src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: finish coding the Intel Gb NIC device src/dev/io_device.hh: we really don't want to be able to pass a null buffer to dma read, at least not the way we have things setup now... it won't work at all 4022:c422464ca16e Wed Feb 07 13:53:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Make memory commands dense again to avoid cache stat table explosion. Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc |
H A D | io_device.cc | 4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch 4885:385a051ad874 Sat Jul 14 03:09:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Merge of DPRINTF fixes from head. 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4739:9f8edf47aeca Sat Jul 14 14:48:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix & tweak DPRINTFs for tracediff w/new cache code. Note that we should *not* print pointer values in DPRINTFs as these needlessly clutter tracediff output. 4475:fb185cc1c845 Tue May 22 02:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Change getDeviceAddressRanges to use bool for snoop arg. 4451:bfb7c7c0b7ea Mon May 14 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add uglyiness to fix dmas src/dev/io_device.cc: extra printing and assertions src/mem/bridge.hh: deal with packets only satisfying part of a request by making many requests src/mem/cache/cache_impl.hh: make the cache try to satisfy a functional request from the cache above it before checking itself 4437:b6e304245729 Wed May 09 22:34:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> update for new reschedule semantics 4435:7da241055348 Wed May 09 18:20:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add a backoff algorithm when nacks are received by devices add seperate response buffers and request queue sizes in bus bridge add delay to respond to a nack in the bus bridge src/dev/i8254xGBe.cc: src/dev/ide_ctrl.cc: src/dev/ns_gige.cc: src/dev/pcidev.hh: src/dev/sinic.cc: add backoff delay parameters src/dev/io_device.cc: src/dev/io_device.hh: add a backoff algorithm when nacks are received. src/mem/bridge.cc: src/mem/bridge.hh: add seperate response buffers and request queue sizes add a new parameters to specify how long before a nack in ready to go after a packet that needs to be nacked is received src/mem/cache/cache_impl.hh: assert on the src/mem/tport.cc: add a friendly assert to make sure the packet was inserted into the list |
/gem5/src/sim/ | ||
H A D | process.hh | 5282:2dba627b6646 Thu Nov 29 00:22:00 EST 2007 Rick Strong <rstrong@cs.ucsd.edu> Serialization: Fix serialization of file descriptors. Make sure open file descriptors are reopened and the file pointer is in the same place as when the checkpoint occured. Signed-off by: Ali Saidi 5183:b4decf133fe4 Thu Oct 25 20:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore. 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4793:315e1db6bd39 Sun Jul 29 04:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Initial stack frame fixes and constant shuffling. The initial stack frame for x86 is now substantially more correct. The fixes made here can be back ported to SPARC and possible the other ISAs as well. The auxiliary vector types were moved to the LiveProcess base class because they are independent of ISA. Some of the types may only apply to Linux, though, so they may have to be moved. 4434:2ea7b6e0b78f Wed May 09 15:37:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fix the translating ports so it can add a page on a fault 4117:2807cee7b892 Fri Mar 02 22:34:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fix some issues with 32 bit processes. 4111:65fffcb4fae9 Wed Feb 28 11:36:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running. 3971:e935846cccfa Tue Jan 23 01:22:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Added remote gdb objects to each process |
H A D | process.cc | 5282:2dba627b6646 Thu Nov 29 00:22:00 EST 2007 Rick Strong <rstrong@cs.ucsd.edu> Serialization: Fix serialization of file descriptors. Make sure open file descriptors are reopened and the file pointer is in the same place as when the checkpoint occured. Signed-off by: Ali Saidi 5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. 5183:b4decf133fe4 Thu Oct 25 20:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore. 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 5109:386c765572f5 Tue Oct 02 21:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Remote GDB: Turn on remote gdb in SE mode. 5089:26461daa3819 Tue Sep 25 23:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Loader: Only complain about TLS sections if you're using Alpha. 5070:3d6a1e37b944 Tue Sep 11 00:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Loader: Error if a TLS section is found in the binary. 5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors. SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4772:f08370a81812 Fri Jul 27 01:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix argument register indexing. Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. |
H A D | faults.hh | 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. 4695:a63378aed062 Wed Jul 18 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make name, isMachineCheckFault, and isAlignmentFault const. 4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. |
/gem5/src/arch/alpha/ | ||
H A D | faults.cc | 5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system. 5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures. 4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg |
H A D | interrupts.hh | 4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg 4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore 3895:5e8f0e3aeca2 Mon Jan 08 20:50:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> pagetable.hh: small fix so ALPHA_FS will build on macs interrupts.hh: small fix for alpha compile src/arch/alpha/interrupts.hh: small fix for alpha compile src/arch/alpha/pagetable.hh: small fix so ALPHA_FS will build on macs |
H A D | isa_traits.hh | 5228:b08c9c42907a Thu Nov 08 21:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. 4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. 4772:f08370a81812 Fri Jul 27 01:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix argument register indexing. Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. |
/gem5/tests/ | ||
H A D | SConscript | 4937:04ace9ab855e Fri Aug 03 18:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> tests: replace all dest ref files on upgrade (if possible). Originally we were copying all source files in, but this caused problems when (large) inputs were copied along with outputs. Then we switched to just copying the standard files (m5stats.txt, etc.) but that was missing things like the *.console files. This fix should catch all the non-standard files too as long as they are copied in manually once when the test is set up. Also get a lot nicer about warning when files are ignored, and warn when expected files are missing. Those new Python sets sure are handy. 4936:b05a404dce16 Fri Aug 03 18:03:00 EDT 2007 Steve Reinhardt <stever@gmail.com> tests: config.out no longer exists, eliminate ref copy. 4781:59a75bd0ddf4 Sat Jul 28 19:49:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: Check/Fix whitespace on SCons files 4130:a611c874376e Sat Mar 03 22:45:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add a sparc fs regression src/dev/sparc/iob.cc: don't warn on cpu restart/idle/halt stuff tests/SConscript: add sparc target in test Sconscript util/regress: Add SPARC_FS target in regress 4019:cdfb21ba304e Wed Feb 07 00:16:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Add short memtest run to quick regressions. Caveats: - Even though memtest is ISA-independent, it will only run for the Alpha builds, since there's no way to specify ISA-independent reference files and I didn't want to commit 3 copies since I'm not sure we want to run it for all the different ISAs anyway. - Reference outputs were generated on my laptop, so performance numbers will be low compared to zizzer. |
/gem5/src/arch/ | ||
H A D | SConscript | 5228:b08c9c42907a Thu Nov 08 21:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs. 4781:59a75bd0ddf4 Sat Jul 28 19:49:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: Check/Fix whitespace on SCons files 4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 src/arch/mips/utility.hh: src/arch/x86/SConscript: Hand merge 4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it automatic. The point is that now a subdirectory can be added to the build process just by creating a SConscript file in it. The process has two passes. On the first pass, all subdirs of the root of the tree are searched for SConsopts files. These files contain any command line options that ought to be added for a particular subdirectory. On the second pass, all subdirs of the src directory are searched for SConscript files. These files describe how to build any given subdirectory. I have added a Source() function. Any file (relative to the directory in which the SConscript resides) passed to that function is added to the build. Clean up everything to take advantage of Source(). function is added to the list of files to be built. 4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. |
/gem5/src/arch/mips/linux/ | ||
H A D | process.cc | 5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers 5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". |
/gem5/tests/configs/ | ||
H A D | simple-atomic-mp.py | 4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object. 4444:0648bdc8d1c9 Thu May 10 18:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs 4390:76bbcf725852 Sun Apr 22 14:39:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update configs to set the CPU clock properly. |
H A D | simple-timing-mp.py | 4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object. 4444:0648bdc8d1c9 Thu May 10 18:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs 4390:76bbcf725852 Sun Apr 22 14:39:00 EDT 2007 Kevin Lim <ktlim@umich.edu> Update configs to set the CPU clock properly. |
/gem5/src/arch/mips/isa/ | ||
H A D | operands.isa | 5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers 5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode 4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1 src/arch/mips/SConscript: "mips import pt.1". |
/gem5/src/arch/sparc/isa/formats/ | ||
H A D | integerop.isa | 5093:7f20bc69fda5 Tue Sep 25 23:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Long overdue cleanup of the condition code handlers. 3980:9bcb2a2e9bb8 Sat Jan 27 01:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc |
/gem5/src/arch/x86/ | ||
H A D | process.hh | 5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack. 4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it. src/arch/x86/SConscript: Add in process source files. src/arch/x86/isa_traits.hh: Replace magic constant numbers with the x86 register names. src/arch/x86/miscregfile.cc: Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy. src/arch/x86/process.hh: An X86 process class. src/base/loader/elf_object.cc: Add in code to recognize x86 as an architecture. src/base/traceflags.py: Add an x86 traceflag src/sim/process.cc: Add in code to create an x86 process. src/arch/x86/intregs.hh: A file which declares names for the integer register indices. src/arch/x86/linux/linux.cc: src/arch/x86/linux/linux.hh: A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either. src/arch/x86/linux/process.cc: src/arch/x86/linux/process.hh: An x86 linux process. The syscall table is split out into it's own file. src/arch/x86/linux/syscalls.cc: The x86 Linux syscall table and the uname function. src/arch/x86/process.cc: The x86 process base class. tests/test-progs/hello/bin/x86/linux/hello: An x86 hello world test binary. 4120:3e09b5d32c45 Sat Mar 03 11:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add build hooks for x86. |
/gem5/src/python/m5/ | ||
H A D | params.py | 5219:e93a04703f56 Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Python: Allow a range to be a python tuple/list. 5037:f7af52292c45 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> python: Write configuration file without reassigning sys.stdout. Using print >>ini_file syntax instead of reassigning sys.stdout allows the python debugger to be used. 5033:2a48ab2b86d5 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> python: Eliminate the Python use of eval() and frame manipulation 4859:97c7749896a6 Fri Aug 03 01:50:00 EDT 2007 Nathan Binkert <nate@binkert.org> python: Improve support for python calling back to C++ member functions. Add support for declaring SimObjects to swig so their members can be wrapped. Make sim_object.i only contain declarations for SimObject. Create system.i to contain declarations for System. Update python code to properly call the C++ given the new changes. 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. 4446:9f5df8033a44 Fri May 11 14:48:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Float should have a c++ param type 4380:1cbb5d3e4288 Thu Apr 12 11:37:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Fix NextEthernetAddr. unproxy() needs to return a new object otherwise all instances will use the same value. This fix is more or less unique to NextEthernetAddr because its use of the proxy stuff is a bit different than everything else. 4168:846a831f6c0b Tue Mar 06 14:16:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Python parameters types need analogous C++ types 4167:ce5d0f62f13b Tue Mar 06 14:13:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. 4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files so things are organized in a more sensible manner. Take apart finalInit and expose the individual functions which are now called from python. Make checkpointing a bit easier to use. |
H A D | simulate.py | 5037:f7af52292c45 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> python: Write configuration file without reassigning sys.stdout. Using print >>ini_file syntax instead of reassigning sys.stdout allows the python debugger to be used. 4946:fa62733fca2d Sat Aug 04 19:09:00 EDT 2007 Nathan Binkert <nate@binkert.org> switching: Remove the drain and resume code from the switching code. This allows us to change memory modes as well. Clean up the code while we're at it. 4945:6f40bdb0ba9f Sat Aug 04 19:06:00 EDT 2007 Nathan Binkert <nate@binkert.org> python: use the enum values in the memory mode changing code 4859:97c7749896a6 Fri Aug 03 01:50:00 EDT 2007 Nathan Binkert <nate@binkert.org> python: Improve support for python calling back to C++ member functions. Add support for declaring SimObjects to swig so their members can be wrapped. Make sim_object.i only contain declarations for SimObject. Create system.i to contain declarations for System. Update python code to properly call the C++ given the new changes. 4851:af527e8042bd Thu Aug 02 03:03:00 EDT 2007 Nathan Binkert <nate@binkert.org> python: need to import objects to make some calls work 4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. |
/gem5/src/mem/ | ||
H A D | port.cc | 5283:3ab643fa74be Wed Nov 28 17:39:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make ports that aren't connected to anything fail more gracefully. 4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are now encoded in cmd field. 4321:6f8b597ab244 Wed Apr 04 13:56:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> The MemoryObject tha owns a port should delete it if it so chooses when deletePortRefs() is called on it with that port as a parameter. In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather than creating a new one each time. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/cache_impl.hh: only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc) 4190:5069dfa3d62e Thu Mar 08 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> stop m5 from leaking like a sieve don't create a new physPort/virtPort every time activateContext() is called add the ability to tell a memory object to delete it's reference to a port and a method to have a port call deletePortRefs() on the port owner as well as delete it's peer still need to stop calling connectMemoPorts() every time activateContext() is called or we'll overflow the bus id and panic src/cpu/thread_state.cc: if we hav ea (phys|virt)Port don't create a new on, have it delete it's peer and then reuse it src/mem/bus.cc: src/mem/bus.hh: add ability to delete a port by usig a hash_map instead of an array to store port ids add a function to do deleting src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/mem_object.cc: src/mem/mem_object.hh: adda function to delete port references from a memory object src/mem/port.cc: src/mem/port.hh: add a removeConn function that tell the owener to delete any references to the port and then deletes its peer 4022:c422464ca16e Wed Feb 07 13:53:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Make memory commands dense again to avoid cache stat table explosion. Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. 3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc |
Completed in 372 milliseconds