Searched defs:latency (Results 1 - 25 of 43) sorted by relevance

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/gem5/src/mem/ruby/network/
H A D	BasicRouter.py	40 latency = Param.Cycles(1, "number of cycles inside router") variable in class:BasicRouter
H A D	BasicLink.py	37 latency = Param.Cycles(1, "latency") variable in class:BasicLink
/gem5/src/learning_gem5/part2/
H A D	hello_object.hh	58 const Tick latency; member in class:HelloObject
H A D	SimpleCache.py	43 latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss") variable in class:SimpleCache
H A D	simple_cache.hh	266 const Cycles latency; member in class:SimpleCache
/gem5/src/mem/
H A D	SimpleMemory.py	49 latency = Param.Latency('30ns', "Request to response latency") variable in class:SimpleMemory
H A D	tport.cc	73 Tick latency = recvAtomic(pkt); local
H A D	dram_ctrl.cc	275 Tick latency = 0; local [all...]
H A D	simple_mem.hh	109 const Tick latency; member in class:SimpleMemory
H A D	noncoherent_xbar.cc	219 Tick latency = pkt->headerDelay; local
/gem5/src/dev/x86/
H A D	i8237.hh	43 Tick latency; member in class:X86ISA::I8237
H A D	speaker.hh	46 Tick latency; member in class:X86ISA::Speaker
H A D	cmos.hh	45 Tick latency; member in class:X86ISA::Cmos
H A D	i8259.hh	50 Tick latency; member in class:X86ISA::I8259
H A D	i8254.hh	45 Tick latency; member in class:X86ISA::I8254
H A D	intdev.hh	96 Tick latency; member in class:X86ISA::IntMasterPort
/gem5/configs/ruby/
H A D	AMD_Base_Constructor.py	50 latency = 1 variable in class:L1Cache 61 latency = 10 variable in class:L2Cache
/gem5/tests/gem5/memory/
H A D	simple-run.py	63 latency = args.latency variable in class:MyMem
/gem5/src/mem/ruby/system/
H A D	VIPERCoalescer.cc	222 Tick latency = cyclesToTicks( local 253 Tick latency = cyclesToTicks( local 281 Tick latency = cyclesToTicks( local 297 Tick latency local [all...]
/gem5/src/mem/qos/
H A D	mem_ctrl.cc	189 double latency = (double) (curTick() + delay - requestTime) local [all...]
/gem5/tests/gem5/cpu_tests/
H A D	run.py	95 latency = '1ns' variable in class:MySimpleMemory
/gem5/configs/splash2/
H A D	run.py	163 latency = options.l1latency variable in class:L1 172 latency = options.l2latency variable in class:L2
H A D	cluster.py	142 latency = options.l1latency variable in class:L1 151 latency = options.l2latency variable in class:L2
/gem5/src/mem/cache/
H A D	noncoherent_cache.cc	181 Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); local
/gem5/src/mem/cache/prefetch/
H A D	queued.hh	152 const Cycles latency; member in class:QueuedPrefetcher

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Indexes created Thu Sep 26 06:36:22 EDT 2019