15633Sgblack@eecs.umich.edu/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 145633Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 155633Sgblack@eecs.umich.edu * All rights reserved. 165633Sgblack@eecs.umich.edu * 175633Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 185633Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 195633Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 205633Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 215633Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 225633Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 235633Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 245633Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 255633Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265633Sgblack@eecs.umich.edu * this software without specific prior written permission. 275633Sgblack@eecs.umich.edu * 285633Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295633Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305633Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315633Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325633Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335633Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345633Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355633Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365633Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375633Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385633Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395633Sgblack@eecs.umich.edu * 405633Sgblack@eecs.umich.edu * Authors: Gabe Black 415633Sgblack@eecs.umich.edu */ 425633Sgblack@eecs.umich.edu 435633Sgblack@eecs.umich.edu#ifndef __DEV_X86_INTDEV_HH__ 445633Sgblack@eecs.umich.edu#define __DEV_X86_INTDEV_HH__ 455633Sgblack@eecs.umich.edu 466216Snate@binkert.org#include <cassert> 478229Snate@binkert.org#include <list> 485651Sgblack@eecs.umich.edu#include <string> 495633Sgblack@eecs.umich.edu 508229Snate@binkert.org#include "arch/x86/intmessage.hh" 515651Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 5214295Sgabeblack@google.com#include "mem/tport.hh" 535633Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 546138Sgblack@eecs.umich.edu 5514295Sgabeblack@google.comnamespace X86ISA 5614295Sgabeblack@google.com{ 575633Sgblack@eecs.umich.edu 5814294Sgabeblack@google.comtemplate <class Device> 5914294Sgabeblack@google.comclass IntSlavePort : public SimpleTimingPort 6014294Sgabeblack@google.com{ 6114294Sgabeblack@google.com Device * device; 6214294Sgabeblack@google.com 6314294Sgabeblack@google.com public: 6414294Sgabeblack@google.com IntSlavePort(const std::string& _name, SimObject* _parent, 6514294Sgabeblack@google.com Device* dev) : 6614294Sgabeblack@google.com SimpleTimingPort(_name, _parent), device(dev) 6714294Sgabeblack@google.com { 6814294Sgabeblack@google.com } 6914294Sgabeblack@google.com 7014294Sgabeblack@google.com AddrRangeList 7114294Sgabeblack@google.com getAddrRanges() const 7214294Sgabeblack@google.com { 7314294Sgabeblack@google.com return device->getIntAddrRange(); 7414294Sgabeblack@google.com } 7514294Sgabeblack@google.com 7614294Sgabeblack@google.com Tick 7714294Sgabeblack@google.com recvAtomic(PacketPtr pkt) 7814294Sgabeblack@google.com { 7914294Sgabeblack@google.com panic_if(pkt->cmd != MemCmd::MessageReq, 8014294Sgabeblack@google.com "%s received unexpected command %s from %s.\n", 8114294Sgabeblack@google.com name(), pkt->cmd.toString(), getPeer()); 8214294Sgabeblack@google.com pkt->headerDelay = pkt->payloadDelay = 0; 8314294Sgabeblack@google.com return device->recvMessage(pkt); 8414294Sgabeblack@google.com } 8514294Sgabeblack@google.com}; 8614294Sgabeblack@google.com 876138Sgblack@eecs.umich.edutypedef std::list<int> ApicList; 886138Sgblack@eecs.umich.edu 8914295Sgabeblack@google.comtemplate <class Device> 9014295Sgabeblack@google.comclass IntMasterPort : public QueuedMasterPort 9114295Sgabeblack@google.com{ 9214295Sgabeblack@google.com ReqPacketQueue reqQueue; 9314295Sgabeblack@google.com SnoopRespPacketQueue snoopRespQueue; 9414295Sgabeblack@google.com 9514295Sgabeblack@google.com Device* device; 9614295Sgabeblack@google.com Tick latency; 9714295Sgabeblack@google.com 9814295Sgabeblack@google.com public: 9914295Sgabeblack@google.com IntMasterPort(const std::string& _name, SimObject* _parent, 10014295Sgabeblack@google.com Device* dev, Tick _latency) : 10114295Sgabeblack@google.com QueuedMasterPort(_name, _parent, reqQueue, snoopRespQueue), 10214295Sgabeblack@google.com reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this), 10314295Sgabeblack@google.com device(dev), latency(_latency) 10414295Sgabeblack@google.com { 10514295Sgabeblack@google.com } 10614295Sgabeblack@google.com 10714295Sgabeblack@google.com bool 10814295Sgabeblack@google.com recvTimingResp(PacketPtr pkt) override 10914295Sgabeblack@google.com { 11014295Sgabeblack@google.com return device->recvResponse(pkt); 11114295Sgabeblack@google.com } 11214295Sgabeblack@google.com 11314295Sgabeblack@google.com // This is x86 focused, so if this class becomes generic, this would 11414295Sgabeblack@google.com // need to be moved into a subclass. 11514295Sgabeblack@google.com void 11614295Sgabeblack@google.com sendMessage(X86ISA::ApicList apics, TriggerIntMessage message, bool timing) 11714295Sgabeblack@google.com { 11814295Sgabeblack@google.com for (auto id: apics) { 11914295Sgabeblack@google.com PacketPtr pkt = buildIntRequest(id, message); 12014295Sgabeblack@google.com if (timing) { 12114295Sgabeblack@google.com schedTimingReq(pkt, curTick() + latency); 12214295Sgabeblack@google.com // The target handles cleaning up the packet in timing mode. 12314295Sgabeblack@google.com } else { 12414295Sgabeblack@google.com // ignore the latency involved in the atomic transaction 12514295Sgabeblack@google.com sendAtomic(pkt); 12614295Sgabeblack@google.com assert(pkt->isResponse()); 12714295Sgabeblack@google.com // also ignore the latency in handling the response 12814295Sgabeblack@google.com device->recvResponse(pkt); 12914295Sgabeblack@google.com } 13014295Sgabeblack@google.com } 13114295Sgabeblack@google.com } 13214295Sgabeblack@google.com}; 13314295Sgabeblack@google.com 1349807Sstever@gmail.comclass IntDevice 1355633Sgblack@eecs.umich.edu{ 1365651Sgblack@eecs.umich.edu protected: 1378922Swilliam.wang@arm.com 13814295Sgabeblack@google.com IntMasterPort<IntDevice> intMasterPort; 1395651Sgblack@eecs.umich.edu 1405633Sgblack@eecs.umich.edu public: 14113892Sgabeblack@google.com IntDevice(SimObject * parent, Tick latency = 0) : 1428922Swilliam.wang@arm.com intMasterPort(parent->name() + ".int_master", parent, this, latency) 1435651Sgblack@eecs.umich.edu { 1445651Sgblack@eecs.umich.edu } 1455651Sgblack@eecs.umich.edu 1469807Sstever@gmail.com virtual ~IntDevice() 1475633Sgblack@eecs.umich.edu {} 1485651Sgblack@eecs.umich.edu 1497913SBrad.Beckmann@amd.com virtual void init(); 1507913SBrad.Beckmann@amd.com 15114295Sgabeblack@google.com virtual bool 1526064Sgblack@eecs.umich.edu recvResponse(PacketPtr pkt) 1536064Sgblack@eecs.umich.edu { 15411144Sjthestness@gmail.com panic("recvResponse not implemented.\n"); 1556064Sgblack@eecs.umich.edu } 1565633Sgblack@eecs.umich.edu}; 1575633Sgblack@eecs.umich.edu 1587811Ssteve.reinhardt@amd.com} // namespace X86ISA 1595633Sgblack@eecs.umich.edu 1605633Sgblack@eecs.umich.edu#endif //__DEV_X86_INTDEV_HH__ 161