/gem5/src/arch/x86/regs/ |
H A D | msr.hh | 42 typedef std::unordered_map<Addr, MiscRegIndex> MsrMap; 64 bool msrAddrToIndex(MiscRegIndex ®Num, Addr addr);
|
H A D | misc.hh | 102 enum MiscRegIndex enum in namespace:X86ISA 412 static inline MiscRegIndex 416 return (MiscRegIndex)(MISCREG_CR_BASE + index); 419 static inline MiscRegIndex 423 return (MiscRegIndex)(MISCREG_DR_BASE + index); 426 static inline MiscRegIndex 431 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 434 static inline MiscRegIndex 439 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 442 static inline MiscRegIndex [all...] |
H A D | msr.cc | 149 msrAddrToIndex(MiscRegIndex ®Num, Addr addr)
|
/gem5/src/arch/x86/ |
H A D | mmapped_ipr.hh | 64 MiscRegIndex index = (MiscRegIndex)( 81 MiscRegIndex index = (MiscRegIndex)(
|
/gem5/src/arch/arm/kvm/ |
H A D | arm_cpu.hh | 85 const MiscRegIndex idx; 107 ArmISA::MiscRegIndex decodeCoProcReg(uint64_t id) const; 109 ArmISA::MiscRegIndex decodeVFPCtrlReg(uint64_t id) const;
|
H A D | armv8_cpu.hh | 111 MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name, 118 MiscRegIndex idx; 142 static const std::set<MiscRegIndex> deviceRegSet;
|
H A D | arm_cpu.cc | 375 MiscRegIndex 410 ArmISA::MiscRegIndex 530 MiscRegIndex idx(decodeCoProcReg(id)); 574 MiscRegIndex idx(decodeVFPCtrlReg(id)); 652 MiscRegIndex reg(decodeCoProcReg(id)); 705 MiscRegIndex idx(decodeVFPCtrlReg(id)); 791 MiscRegIndex reg(decodeCoProcReg(id)); 845 MiscRegIndex idx(decodeVFPCtrlReg(id));
|
H A D | armv8_cpu.cc | 116 const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = { 189 const MiscRegIndex idx( 379 const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
|
/gem5/src/arch/arm/insts/ |
H A D | misc64.hh | 132 Fault trap(ThreadContext *tc, MiscRegIndex misc_reg, 135 bool checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 138 bool checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 141 bool checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 149 MiscRegIndex dest; 153 OpClass __opClass, MiscRegIndex _dest, 173 MiscRegIndex dest; 178 OpClass __opClass, MiscRegIndex _dest, 192 MiscRegIndex op1; 197 MiscRegIndex _op [all...] |
H A D | misc.hh | 103 MiscRegIndex op1; 109 MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, 124 MiscRegIndex dest; 128 IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest, 275 MiscRegIndex dest; 280 MiscRegIndex _dest, IntRegIndex _op1, 294 MiscRegIndex op1; 298 IntRegIndex _dest, MiscRegIndex _op1, 387 MiscRegIndex miscReg; 391 uint64_t _iss, MiscRegIndex _miscRe [all...] |
H A D | misc64.cc | 87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, 122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
|
H A D | misc.cc | 331 uint64_t _iss, MiscRegIndex _miscReg) 360 MiscRegIndex _miscReg)
|
H A D | mem64.hh | 52 MiscRegIndex dest; 56 IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
|
/gem5/src/arch/arm/ |
H A D | faults.hh | 208 MiscRegIndex getSyndromeReg64() const; 211 MiscRegIndex getFaultAddrReg64() const; 237 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 452 void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) override; 459 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 460 static const MiscRegIndex FarIndex = MISCREG_IFAR; 461 static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 478 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 479 static const MiscRegIndex FarIndex = MISCREG_DFAR; 480 static const MiscRegIndex HFarInde [all...] |
H A D | miscregs.hh | 57 enum MiscRegIndex { enum in namespace:ArmISA 986 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, 988 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1, 992 bool aarch64SysRegReadOnly(MiscRegIndex miscReg); 995 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, 999 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1); 1908 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 1924 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 1928 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1932 bool canWriteAArch64SysReg(MiscRegIndex re [all...] |
H A D | utility.hh | 321 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss); 324 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 327 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
|
H A D | utility.cc | 462 mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss) 602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
|
H A D | isa.hh | 650 flat_idx = snsBankedIndex64((MiscRegIndex)reg, 659 snsBankedIndex64(MiscRegIndex reg, bool ns) const
|
H A D | faults.cc | 350 MiscRegIndex 366 MiscRegIndex 383 ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 622 MiscRegIndex elr_idx, spsr_idx; 978 // SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 1115 AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
|
/gem5/src/arch/power/ |
H A D | miscregs.hh | 39 enum MiscRegIndex { enum in namespace:PowerISA
|
/gem5/src/arch/sparc/ |
H A D | miscregs.hh | 40 enum MiscRegIndex enum in namespace:SparcISA
|
/gem5/src/arch/alpha/ |
H A D | registers.hh | 64 enum MiscRegIndex enum in namespace:AlphaISA
|
/gem5/src/arch/mips/ |
H A D | registers.hh | 132 enum MiscRegIndex{ enum in namespace:MipsISA
|
/gem5/src/arch/riscv/ |
H A D | faults.cc | 85 MiscRegIndex cause, epc, tvec, tval;
|
/gem5/src/dev/arm/ |
H A D | gic_v3_cpu_interface.hh | 341 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const; 342 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
|