1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#ifndef __ARCH_ARM_KVM_ARM_CPU_HH__
41#define __ARCH_ARM_KVM_ARM_CPU_HH__
42
43#include <set>
44#include <vector>
45
46#include "cpu/kvm/base.hh"
47#include "params/ArmKvmCPU.hh"
48
49/**
50 * ARM implementation of a KVM-based hardware virtualized CPU.
51 * Architecture specific limitations:
52 *  * LPAE is currently not supported by gem5. We therefore panic if LPAE
53 *    is enabled when returning to gem5.
54 *  * The co-processor based interface to the architected timer is
55 *    unsupported. We can't support this due to limitations in the KVM
56 *    API on ARM.
57 *  * M5 ops are currently not supported. This requires either a kernel
58 *  hack or a memory mapped device that handles the guest<->m5
59 *  interface.
60 */
61class ArmKvmCPU : public BaseKvmCPU
62{
63  public:
64    ArmKvmCPU(ArmKvmCPUParams *params);
65    virtual ~ArmKvmCPU();
66
67    void startup();
68
69    void dump();
70
71  protected:
72    struct KvmIntRegInfo {
73        /** KVM ID */
74        const uint64_t id;
75        /** gem5 index */
76        const IntRegIndex idx;
77        /** Name in debug output */
78        const char *name;
79    };
80
81    struct KvmCoreMiscRegInfo {
82        /** KVM ID */
83        const uint64_t id;
84        /** gem5 index */
85        const MiscRegIndex idx;
86        /** Name in debug output */
87        const char *name;
88    };
89
90    typedef std::vector<uint64_t> RegIndexVector;
91
92    Tick kvmRun(Tick ticks);
93
94    void updateKvmState();
95    void updateThreadContext();
96
97    Tick onKvmExitHypercall();
98
99    /**
100     * Get a list of registers supported by getOneReg() and setOneReg().
101     */
102    const RegIndexVector &getRegList() const;
103
104    void kvmArmVCpuInit(uint32_t target);
105    void kvmArmVCpuInit(const struct kvm_vcpu_init &init);
106
107    ArmISA::MiscRegIndex decodeCoProcReg(uint64_t id) const;
108
109    ArmISA::MiscRegIndex decodeVFPCtrlReg(uint64_t id) const;
110
111    /**
112     * Determine if a register is invariant.
113     *
114     * Some registers must have the same value in both the host and
115     * the guest. Such registers are referred to as "invariant"
116     * registers in KVM. This is a restriction imposed by KVM as
117     * having different values in ID registers (e.g., the cache
118     * identification registers) would confuse the guest kernel.
119     */
120    bool isInvariantReg(uint64_t id);
121
122    static KvmIntRegInfo kvmIntRegs[];
123    static KvmCoreMiscRegInfo kvmCoreMiscRegs[];
124
125  private:
126    /**
127     * Get a list of registers supported by getOneReg() and setOneReg().
128     *
129     * @return False if the number of elements allocated in the list
130     * is too small to hold the complete register list (the required
131     * value is written into n in this case). True on success.
132     */
133    bool getRegList(struct kvm_reg_list &regs) const;
134
135    void dumpKvmStateCore();
136    void dumpKvmStateMisc();
137    void dumpKvmStateCoProc(uint64_t id);
138    void dumpKvmStateVFP(uint64_t id);
139
140    void updateKvmStateCore();
141    void updateKvmStateMisc();
142    void updateKvmStateCoProc(uint64_t id, bool show_warnings);
143    void updateKvmStateVFP(uint64_t id, bool show_warnings);
144
145    void updateTCStateCore();
146    void updateTCStateMisc();
147    void updateTCStateCoProc(uint64_t id, bool show_warnings);
148    void updateTCStateVFP(uint64_t id, bool show_warnings);
149
150
151    /** Cached state of the IRQ line */
152    bool irqAsserted;
153    /** Cached state of the FIQ line */
154    bool fiqAsserted;
155
156    /**
157     * Cached copy of the list of co-processor registers supported by
158     * KVM
159     */
160    mutable RegIndexVector _regIndexList;
161
162    /**
163     * List of co-processor registers that KVM requires to be
164     * identical on both the host and the guest. KVM does not allow
165     * writes to these registers.
166     */
167    static const std::set<uint64_t> invariant_regs;
168};
169
170#endif // __ARCH_ARM_KVM_ARM_CPU_HH__
171