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/gem5/src/arch/power/insts/
H A Dstatic_inst.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/cpu/
H A Dreg_class.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dreg_class.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dthread_context.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/cpu/o3/
H A Dfree_list.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dregfile.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Drename_map.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dfree_list.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Drename_map.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/x86/insts/
H A Dstatic_inst.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/null/
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/alpha/
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Disa.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dutility.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/power/
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Disa.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dutility.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/sparc/
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Disa.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dutility.ccdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/mips/
H A Disa.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/x86/
H A Disa.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
/gem5/src/arch/arm/
H A Dregisters.hhdiff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.

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