17506Stjones1@inf.ed.ac.uk/* 27506Stjones1@inf.ed.ac.uk * Copyright (c) 2003-2005 The Regents of The University of Michigan 37506Stjones1@inf.ed.ac.uk * Copyright (c) 2007-2008 The Florida State University 47506Stjones1@inf.ed.ac.uk * Copyright (c) 2009 The University of Edinburgh 57506Stjones1@inf.ed.ac.uk * All rights reserved. 67506Stjones1@inf.ed.ac.uk * 77506Stjones1@inf.ed.ac.uk * Redistribution and use in source and binary forms, with or without 87506Stjones1@inf.ed.ac.uk * modification, are permitted provided that the following conditions are 97506Stjones1@inf.ed.ac.uk * met: redistributions of source code must retain the above copyright 107506Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer; 117506Stjones1@inf.ed.ac.uk * redistributions in binary form must reproduce the above copyright 127506Stjones1@inf.ed.ac.uk * notice, this list of conditions and the following disclaimer in the 137506Stjones1@inf.ed.ac.uk * documentation and/or other materials provided with the distribution; 147506Stjones1@inf.ed.ac.uk * neither the name of the copyright holders nor the names of its 157506Stjones1@inf.ed.ac.uk * contributors may be used to endorse or promote products derived from 167506Stjones1@inf.ed.ac.uk * this software without specific prior written permission. 177506Stjones1@inf.ed.ac.uk * 187506Stjones1@inf.ed.ac.uk * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 197506Stjones1@inf.ed.ac.uk * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 207506Stjones1@inf.ed.ac.uk * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 217506Stjones1@inf.ed.ac.uk * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 227506Stjones1@inf.ed.ac.uk * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 237506Stjones1@inf.ed.ac.uk * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 247506Stjones1@inf.ed.ac.uk * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 257506Stjones1@inf.ed.ac.uk * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 267506Stjones1@inf.ed.ac.uk * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 277506Stjones1@inf.ed.ac.uk * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 287506Stjones1@inf.ed.ac.uk * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 297506Stjones1@inf.ed.ac.uk * 307506Stjones1@inf.ed.ac.uk * Authors: Korey Sewell 317506Stjones1@inf.ed.ac.uk * Stephen Hines 327506Stjones1@inf.ed.ac.uk * Timothy M. Jones 337506Stjones1@inf.ed.ac.uk */ 347506Stjones1@inf.ed.ac.uk 357506Stjones1@inf.ed.ac.uk#include "arch/power/utility.hh" 3611793Sbrandon.potter@amd.com 3712334Sgabeblack@google.com#include "base/logging.hh" 387506Stjones1@inf.ed.ac.uk 397506Stjones1@inf.ed.ac.uknamespace PowerISA { 407506Stjones1@inf.ed.ac.uk 417506Stjones1@inf.ed.ac.ukvoid 427506Stjones1@inf.ed.ac.ukcopyRegs(ThreadContext *src, ThreadContext *dest) 437506Stjones1@inf.ed.ac.uk{ 447506Stjones1@inf.ed.ac.uk // First loop through the integer registers. 457506Stjones1@inf.ed.ac.uk for (int i = 0; i < NumIntRegs; ++i) 467506Stjones1@inf.ed.ac.uk dest->setIntReg(i, src->readIntReg(i)); 477506Stjones1@inf.ed.ac.uk 487506Stjones1@inf.ed.ac.uk // Then loop through the floating point registers. 497506Stjones1@inf.ed.ac.uk for (int i = 0; i < NumFloatRegs; ++i) 5013611Sgabeblack@google.com dest->setFloatReg(i, src->readFloatReg(i)); 517506Stjones1@inf.ed.ac.uk 529920Syasuko.eckert@amd.com // Would need to add condition-code regs if implemented 539920Syasuko.eckert@amd.com assert(NumCCRegs == 0); 549920Syasuko.eckert@amd.com 557506Stjones1@inf.ed.ac.uk // Copy misc. registers 567506Stjones1@inf.ed.ac.uk copyMiscRegs(src, dest); 577506Stjones1@inf.ed.ac.uk 587506Stjones1@inf.ed.ac.uk // Lastly copy PC/NPC 597720Sgblack@eecs.umich.edu dest->pcState(src->pcState()); 607506Stjones1@inf.ed.ac.uk} 617506Stjones1@inf.ed.ac.uk 628787Sgblack@eecs.umich.eduuint64_t 638787Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 648787Sgblack@eecs.umich.edu{ 658787Sgblack@eecs.umich.edu panic("getArgument not implemented for POWER.\n"); 668787Sgblack@eecs.umich.edu return 0; 678787Sgblack@eecs.umich.edu} 688787Sgblack@eecs.umich.edu 697693SAli.Saidi@ARM.comvoid 707693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 717693SAli.Saidi@ARM.com{ 727693SAli.Saidi@ARM.com panic("Not Implemented for POWER"); 737693SAli.Saidi@ARM.com} 747693SAli.Saidi@ARM.com 758791Sgblack@eecs.umich.eduvoid 768791Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 778791Sgblack@eecs.umich.edu{ 788791Sgblack@eecs.umich.edu panic("initCPU not implemented for POWER.\n"); 798791Sgblack@eecs.umich.edu} 808791Sgblack@eecs.umich.edu 817693SAli.Saidi@ARM.com 827811Ssteve.reinhardt@amd.com} // namespace PowerISA 83