Searched hist:7222 (Results 1 - 13 of 13) sorted by relevance
/gem5/src/arch/x86/isa/insts/system/ | ||
H A D | segmentation.py | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/x86/insts/ | ||
H A D | static_inst.cc | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/x86/isa/ | ||
H A D | specialize.isa | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
H A D | microasm.isa | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
H A D | operands.isa | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/ | ||
H A D | move.py | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | data.isa | diff 7222:c6c7740edaf3 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode the unsigned 8 and 16 bit add and subtract instructions. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | one_byte_opcodes.isa | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/x86/ | ||
H A D | utility.cc | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
H A D | tlb.cc | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
/gem5/src/arch/arm/ | ||
H A D | utility.cc | diff 12496:e7bc841e521c Wed Jan 03 06:01:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ELUsingAArch32K from armarm pseudocode This patch implements the ELUsingAArch32K pseudocode, which is returning true if the provided Exception Level is using A32 ISA, but it is not panicking (quitting simulation) if the information is unknown (see documentation). The panicking is the current behaviour of the ELIs32 utility in gem5. Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7222 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | utility.hh | diff 12496:e7bc841e521c Wed Jan 03 06:01:00 EST 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: ELUsingAArch32K from armarm pseudocode This patch implements the ELUsingAArch32K pseudocode, which is returning true if the provided Exception Level is using A32 ISA, but it is not panicking (quitting simulation) if the information is unknown (see documentation). The panicking is the current behaviour of the ELIs32 utility in gem5. Change-Id: Iad7b56077d7e0f8ee223b5b9593cb8097f26bb29 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7222 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | regop.isa | diff 5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs. |
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