arm: Fix decoding of CRC32 instructions in thumb32

The CRC32 and CRC32C instructions are incorrectly decoded in thumb32
mode according to the latest manual:
https://developer.arm.com/docs/ddi0597/latest/top-level-encodings-for-t32/16-bit#dpint_2r

Change-Id: I9c6684f1ec7fe14d3b4cdf13f117a9819e046578
Signed-off-by: Chun-Chen TK Hsu
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19028
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: update hint instruction decoding to match ARMv8.5

This fixes:

- unallocated hints that have since been allocated
- unallocated and unimplemented hint instructions being treated as
Unknown instead of the correct NOP
- missing encoding for DBG on A32

Unallocated and unimplemented hints give a warning if executed.

The most important fix was for the CSDB Spectre mitigation
instruction, which was added recently and previously unallocated and
treated as Unknown.

The Linux kernel v4.18 ARMv7 uses CSDB it and boot would
fail with "undefined instruction" since Linux commit
1d4238c56f9816ce0f9c8dbe42d7f2ad81cb6613

Change-Id: I283da3f08a9af4148edc6fb3ca2930cbb97126b8
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13475
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Fix implicit-fallthrough warnings when building with gcc-7+

gcc 7 onwards have additional heuristics to detect implicit
fallthroughs and it fails the build with warnings for ARM as a result.
There was one gcc bug[1] that I fixed but the rest are cases that gcc
cannot detect due to the point at which it does the fallthrough check.
Most of this patch adds __builtin_unreachable() hints in places that throw
this warning to indicate to gcc that the fallthrough will never
happen.

The remaining cases are actually possible fallthroughs due to
incorrect code running on the simulator; in which case an Unknown
instruction is returned.

[1] https://gcc.gnu.org/ml/gcc-patches/2018-02/msg01105.html

Change-Id: I1baa9fa0ed15181c10c755c0bd777f88b607c158
Signed-off-by: Siddhesh Poyarekar <siddhesh.poyarekar@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/8541
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Add AArch32 HLT Semihosting interface

AArch32 HLT instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: I77da73d2e6a9288c704a5f646f4447022517ceb6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8372
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for armv8 CRC32 instructions

This patch introduces the ARM A32/T32/A64 CRC Instructions, which are
mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as
follows:
1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32
2) The instructions support predication in Aarch32
3) Using R15(PC) as source/dest operand is permitted in Aarch32

Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5521
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

ARM: Clean up condCodes in IT blocks.

SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.

ARM: BX instruction can be contitional if last instruction in a IT block

Branches are allowed to be the last instuction in an IT block. Before it was
assumed that they could not. So Branches in thumb2 were Uncond.

ARM: Combine some redundant cases in one of the data decode functions.

ARM: Hook the misc instructions into the thumb decoder.

ARM: Move some miscellaneous instructions out of the decoder to share with thumb.

ARM: Implement the bkpt instruction.

ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.

ARM: Decode the CPS instruction.

ARM: Decode the setend instruction.

ARM: Make sure some undefined thumb32 instructions fault.

ARM: Decode the bfi and bfc instructions.

ARM: Decode the ubfx and sbfx instructions.

ARM: Decode miscellaneous arm mode media instructions.

ARM: Decode the clz instruction.

ARM: Decode the rbit instruction.

ARM: Decode the nop instruction.

ARM: Decode the usad8 and usada8 instructions.

ARM: Decode the sel instruction.

ARM: Decode pkh instructions.

ARM: Decode the sign/zero extend instructions.

ARM: Decode the 8/16 bit signed/unsigned add/subtract half instructions.

ARM: Decode the saturation instructions.

ARM: Decode the signed add/subtract and subtract/add instructions.

ARM: Decode the unsigned 8 and 16 bit add and subtract instructions.

ARM: Decode the unsigned saturating instructions.

ARM: Decode the ssub instructions.

ARM: Decode the SADD8 and SADD16 instructions.

ARM: Decode 32 bit thumb data processing register instructions.

ARM: Decode the 16 bit thumb versions of the REV* instructions.

ARM: Decode the ARM version of the REV* instructions.

ARM: Pull decoding of ARM pack, unpack, saturate and reverse instructions into a format.

ARM: Hook up the push/pop versions of stm/ldm in thumb.

ARM: Decode the scalar saturating add/subtract instructions.

ARM: Decode the parallel add and subtract instructions.

ARM: Add support for "SUBS PC, LR and related instructions".

ARM: Implement ADR as separate from ADD.

ARM: Fix when the flag bits are updated for thumb.

ARM: Remove special naming for the new version of multiply.

ARM: Hook the new multiply instructions into all the decoders.

ARM: Decode plain binary immediate thumb data processing instructions.

ARM: Hook the new branch instructions into the 16 bit thumb decoder.

ARM: Remove the special naming from the new version of data processing instructions.

ARM: Hook the external data processing instructions into the Thumb decoder.

ARM: Hook the new external data processing instructions to the ARM decoder.