data.isa revision 7258:6e8a3c0a2a40
1// Copyright (c) 2010 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Redistribution and use in source and binary forms, with or without 14// modification, are permitted provided that the following conditions are 15// met: redistributions of source code must retain the above copyright 16// notice, this list of conditions and the following disclaimer; 17// redistributions in binary form must reproduce the above copyright 18// notice, this list of conditions and the following disclaimer in the 19// documentation and/or other materials provided with the distribution; 20// neither the name of the copyright holders nor the names of its 21// contributors may be used to endorse or promote products derived from 22// this software without specific prior written permission. 23// 24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35// 36// Authors: Gabe Black 37 38def format ArmMiscMedia() {{ 39 decode_block = ''' 40 { 41 const uint32_t op1 = bits(machInst, 22, 20); 42 const uint32_t op2 = bits(machInst, 7, 5); 43 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 44 const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 45 if (op1 == 0 && op2 == 0) { 46 const IntRegIndex rd = 47 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 48 const IntRegIndex rm = 49 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 50 if (ra == 0xf) { 51 return new Usad8(machInst, rd, rn, rm); 52 } else { 53 return new Usada8(machInst, rd, rn, rm, ra); 54 } 55 } else if (bits(op2, 1, 0) == 0x2) { 56 const uint32_t lsb = bits(machInst, 11, 7); 57 const uint32_t msb = lsb + bits(machInst, 20, 16); 58 if (bits(op1, 2, 1) == 0x3) { 59 return new Ubfx(machInst, ra, rn, lsb, msb); 60 } else if (bits(op1, 2, 1) == 0x1) { 61 return new Sbfx(machInst, ra, rn, lsb, msb); 62 } 63 } else if (bits(op2, 1, 0) == 0x0 && bits(op1, 2, 1) == 0x2) { 64 const uint32_t lsb = bits(machInst, 11, 7); 65 const uint32_t msb = bits(machInst, 20, 16); 66 if (rn == 0xf) { 67 return new Bfc(machInst, ra, ra, lsb, msb); 68 } else { 69 return new Bfi(machInst, ra, rn, lsb, msb); 70 } 71 } 72 return new Unknown(machInst); 73 } 74 ''' 75}}; 76 77def format ArmDataProcReg() {{ 78 pclr = ''' 79 return new %(className)ssRegPclr(machInst, %(dest)s, 80 %(op1)s, rm, imm5, 81 type); 82 ''' 83 instDecode = ''' 84 case %(opcode)#x: 85 if (immShift) { 86 if (setCc) { 87 if (%(dest)s == INTREG_PC) { 88 %(pclr)s 89 } else { 90 return new %(className)sRegCc(machInst, %(dest)s, 91 %(op1)s, rm, imm5, type); 92 } 93 } else { 94 return new %(className)sReg(machInst, %(dest)s, %(op1)s, 95 rm, imm5, type); 96 } 97 } else { 98 if (setCc) { 99 return new %(className)sRegRegCc(machInst, %(dest)s, 100 %(op1)s, rm, rs, type); 101 } else { 102 return new %(className)sRegReg(machInst, %(dest)s, 103 %(op1)s, rm, rs, type); 104 } 105 } 106 break; 107 ''' 108 109 def instCode(opcode, mnem, useDest = True, useOp1 = True): 110 global pclr 111 if useDest: 112 dest = "rd" 113 else: 114 dest = "INTREG_ZERO" 115 if useOp1: 116 op1 = "rn" 117 else: 118 op1 = "INTREG_ZERO" 119 global instDecode, pclrCode 120 substDict = { "className": mnem.capitalize(), 121 "opcode": opcode, 122 "dest": dest, 123 "op1": op1 } 124 if useDest: 125 substDict["pclr"] = pclr % substDict 126 else: 127 substDict["pclr"] = "" 128 return instDecode % substDict 129 130 decode_block = ''' 131 { 132 const bool immShift = (bits(machInst, 4) == 0); 133 const bool setCc = (bits(machInst, 20) == 1); 134 const uint32_t imm5 = bits(machInst, 11, 7); 135 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 136 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 137 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 138 const IntRegIndex rm = (IntRegIndex)(uint32_t)RM; 139 const IntRegIndex rs = (IntRegIndex)(uint32_t)RS; 140 switch (OPCODE) { 141 ''' 142 decode_block += instCode(0x0, "and") 143 decode_block += instCode(0x1, "eor") 144 decode_block += instCode(0x2, "sub") 145 decode_block += instCode(0x3, "rsb") 146 decode_block += instCode(0x4, "add") 147 decode_block += instCode(0x5, "adc") 148 decode_block += instCode(0x6, "sbc") 149 decode_block += instCode(0x7, "rsc") 150 decode_block += instCode(0x8, "tst", useDest = False) 151 decode_block += instCode(0x9, "teq", useDest = False) 152 decode_block += instCode(0xa, "cmp", useDest = False) 153 decode_block += instCode(0xb, "cmn", useDest = False) 154 decode_block += instCode(0xc, "orr") 155 decode_block += instCode(0xd, "mov", useOp1 = False) 156 decode_block += instCode(0xe, "bic") 157 decode_block += instCode(0xf, "mvn", useOp1 = False) 158 decode_block += ''' 159 default: 160 return new Unknown(machInst); 161 } 162 } 163 ''' 164}}; 165 166def format ArmPackUnpackSatReverse() {{ 167 decode_block = ''' 168 { 169 const uint32_t op1 = bits(machInst, 22, 20); 170 const uint32_t a = bits(machInst, 19, 16); 171 const uint32_t op2 = bits(machInst, 7, 5); 172 if (bits(op2, 0) == 0) { 173 const IntRegIndex rn = 174 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 175 const IntRegIndex rd = 176 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 177 const uint32_t satImm = bits(machInst, 20, 16); 178 const uint32_t imm = bits(machInst, 11, 7); 179 const ArmShiftType type = 180 (ArmShiftType)(uint32_t)bits(machInst, 6, 5); 181 if (op1 == 0) { 182 if (type) { 183 return new PkhtbReg(machInst, rd, (IntRegIndex)a, 184 rn, imm, type); 185 } else { 186 return new PkhbtReg(machInst, rd, (IntRegIndex)a, 187 rn, imm, type); 188 } 189 } else if (bits(op1, 2, 1) == 1) { 190 return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 191 } else if (bits(op1, 2, 1) == 3) { 192 return new Usat(machInst, rd, satImm, rn, imm, type); 193 } 194 return new Unknown(machInst); 195 } 196 switch (op1) { 197 case 0x0: 198 { 199 const IntRegIndex rn = 200 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 201 const IntRegIndex rd = 202 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 203 const IntRegIndex rm = 204 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 205 if (op2 == 0x3) { 206 const uint32_t rotation = 207 (uint32_t)bits(machInst, 11, 10) << 3; 208 if (a == 0xf) { 209 return new Sxtb16(machInst, rd, rotation, rm); 210 } else { 211 return new Sxtab16(machInst, rd, rn, rm, rotation); 212 } 213 } else if (op2 == 0x5) { 214 return new Sel(machInst, rd, rn, rm); 215 } 216 } 217 break; 218 case 0x2: 219 if (op2 == 0x1) { 220 const IntRegIndex rn = 221 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 222 const IntRegIndex rd = 223 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 224 const uint32_t satImm = bits(machInst, 20, 16); 225 return new Ssat16(machInst, rd, satImm + 1, rn); 226 } else if (op2 == 0x3) { 227 const IntRegIndex rn = 228 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 229 const IntRegIndex rd = 230 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 231 const IntRegIndex rm = 232 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 233 const uint32_t rotation = 234 (uint32_t)bits(machInst, 11, 10) << 3; 235 if (a == 0xf) { 236 return new Sxtb(machInst, rd, rotation, rm); 237 } else { 238 return new Sxtab(machInst, rd, rn, rm, rotation); 239 } 240 } 241 break; 242 case 0x3: 243 if (op2 == 0x1) { 244 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 245 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 246 return new Rev(machInst, rd, rm); 247 } else if (op2 == 0x3) { 248 const IntRegIndex rn = 249 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 250 const IntRegIndex rd = 251 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 252 const IntRegIndex rm = 253 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 254 const uint32_t rotation = 255 (uint32_t)bits(machInst, 11, 10) << 3; 256 if (a == 0xf) { 257 return new Sxth(machInst, rd, rotation, rm); 258 } else { 259 return new Sxtah(machInst, rd, rn, rm, rotation); 260 } 261 } else if (op2 == 0x5) { 262 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 263 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 264 return new Rev16(machInst, rd, rm); 265 } 266 break; 267 case 0x4: 268 if (op2 == 0x3) { 269 const IntRegIndex rn = 270 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 271 const IntRegIndex rd = 272 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 273 const IntRegIndex rm = 274 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 275 const uint32_t rotation = 276 (uint32_t)bits(machInst, 11, 10) << 3; 277 if (a == 0xf) { 278 return new Uxtb16(machInst, rd, rotation, rm); 279 } else { 280 return new Uxtab16(machInst, rd, rn, rm, rotation); 281 } 282 } 283 break; 284 case 0x6: 285 if (op2 == 0x1) { 286 const IntRegIndex rn = 287 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 288 const IntRegIndex rd = 289 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 290 const uint32_t satImm = bits(machInst, 20, 16); 291 return new Usat16(machInst, rd, satImm, rn); 292 } else if (op2 == 0x3) { 293 const IntRegIndex rn = 294 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 295 const IntRegIndex rd = 296 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 297 const IntRegIndex rm = 298 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 299 const uint32_t rotation = 300 (uint32_t)bits(machInst, 11, 10) << 3; 301 if (a == 0xf) { 302 return new Uxtb(machInst, rd, rotation, rm); 303 } else { 304 return new Uxtab(machInst, rd, rn, rm, rotation); 305 } 306 } 307 break; 308 case 0x7: 309 { 310 const IntRegIndex rn = 311 (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 312 const IntRegIndex rd = 313 (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 314 const IntRegIndex rm = 315 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 316 if (op2 == 0x1) { 317 return new Rbit(machInst, rd, rm); 318 } else if (op2 == 0x3) { 319 const uint32_t rotation = 320 (uint32_t)bits(machInst, 11, 10) << 3; 321 if (a == 0xf) { 322 return new Uxth(machInst, rd, rotation, rm); 323 } else { 324 return new Uxtah(machInst, rd, rn, rm, rotation); 325 } 326 } else if (op2 == 0x5) { 327 return new Revsh(machInst, rd, rm); 328 } 329 } 330 break; 331 } 332 return new Unknown(machInst); 333 } 334 ''' 335}}; 336 337def format ArmParallelAddSubtract() {{ 338 decode_block=''' 339 { 340 const uint32_t op1 = bits(machInst, 21, 20); 341 const uint32_t op2 = bits(machInst, 7, 5); 342 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 343 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 344 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 345 if (bits(machInst, 22) == 0) { 346 switch (op1) { 347 case 0x1: 348 switch (op2) { 349 case 0x0: 350 return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL); 351 case 0x1: 352 return new SasxRegCc(machInst, rd, rn, rm, 0, LSL); 353 case 0x2: 354 return new SsaxRegCc(machInst, rd, rn, rm, 0, LSL); 355 case 0x3: 356 return new Ssub16RegCc(machInst, rd, rn, rm, 0, LSL); 357 case 0x4: 358 return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL); 359 case 0x7: 360 return new Ssub8RegCc(machInst, rd, rn, rm, 0, LSL); 361 } 362 break; 363 case 0x2: 364 switch (op2) { 365 case 0x0: 366 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 367 case 0x1: 368 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 369 case 0x2: 370 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 371 case 0x3: 372 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 373 case 0x4: 374 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 375 case 0x7: 376 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 377 } 378 break; 379 case 0x3: 380 switch (op2) { 381 case 0x0: 382 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 383 case 0x1: 384 return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 385 case 0x2: 386 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 387 case 0x3: 388 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 389 case 0x4: 390 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 391 case 0x7: 392 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 393 } 394 break; 395 } 396 } else { 397 switch (op1) { 398 case 0x1: 399 switch (op2) { 400 case 0x0: 401 return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL); 402 case 0x1: 403 return new UasxRegCc(machInst, rd, rn, rm, 0, LSL); 404 case 0x2: 405 return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL); 406 case 0x3: 407 return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL); 408 case 0x4: 409 return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL); 410 case 0x7: 411 return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL); 412 } 413 break; 414 case 0x2: 415 switch (op2) { 416 case 0x0: 417 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 418 case 0x1: 419 return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 420 case 0x2: 421 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 422 case 0x3: 423 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 424 case 0x4: 425 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 426 case 0x7: 427 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 428 } 429 break; 430 case 0x3: 431 switch (op2) { 432 case 0x0: 433 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 434 case 0x1: 435 return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 436 case 0x2: 437 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 438 case 0x3: 439 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 440 case 0x4: 441 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 442 case 0x7: 443 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 444 } 445 break; 446 } 447 } 448 return new Unknown(machInst); 449 } 450 ''' 451}}; 452 453def format ArmDataProcImm() {{ 454 pclr = ''' 455 return new %(className)ssImmPclr(machInst, %(dest)s, 456 %(op1)s, imm, false); 457 ''' 458 adr = ''' 459 return new AdrImm(machInst, %(dest)s, %(add)s, 460 imm, false); 461 ''' 462 instDecode = ''' 463 case %(opcode)#x: 464 if (setCc) { 465 if (%(pclrInst)s && %(dest)s == INTREG_PC) { 466 %(pclr)s 467 } else { 468 return new %(className)sImmCc(machInst, %(dest)s, %(op1)s, 469 imm, rotC); 470 } 471 } else { 472 if (%(adrInst)s && %(op1)s == INTREG_PC) { 473 %(adr)s 474 } else { 475 return new %(className)sImm(machInst, %(dest)s, %(op1)s, 476 imm, rotC); 477 } 478 } 479 break; 480 ''' 481 482 def instCode(opcode, mnem, useDest = True, useOp1 = True): 483 global instDecode, pclr, adr 484 if useDest: 485 dest = "rd" 486 else: 487 dest = "INTREG_ZERO" 488 if useOp1: 489 op1 = "rn" 490 else: 491 op1 = "INTREG_ZERO" 492 substDict = { "className": mnem.capitalize(), 493 "opcode": opcode, 494 "dest": dest, 495 "op1": op1, 496 "adr": "", 497 "adrInst": "false" } 498 if useDest: 499 substDict["pclrInst"] = "true" 500 substDict["pclr"] = pclr % substDict 501 else: 502 substDict["pclrInst"] = "false" 503 substDict["pclr"] = "" 504 return instDecode % substDict 505 506 def adrCode(opcode, mnem, add="1"): 507 global instDecode, pclr, adr 508 substDict = { "className": mnem.capitalize(), 509 "opcode": opcode, 510 "dest": "rd", 511 "op1": "rn", 512 "add": add, 513 "pclrInst": "true", 514 "adrInst": "true" } 515 substDict["pclr"] = pclr % substDict 516 substDict["adr"] = adr % substDict 517 return instDecode % substDict 518 519 decode_block = ''' 520 { 521 const bool setCc = (bits(machInst, 20) == 1); 522 const uint32_t unrotated = bits(machInst, 7, 0); 523 const uint32_t rotation = (bits(machInst, 11, 8) << 1); 524 const bool rotC = (rotation != 0); 525 const uint32_t imm = rotate_imm(unrotated, rotation); 526 const IntRegIndex rd = (IntRegIndex)(uint32_t)RD; 527 const IntRegIndex rn = (IntRegIndex)(uint32_t)RN; 528 switch (OPCODE) { 529 ''' 530 decode_block += instCode(0x0, "and") 531 decode_block += instCode(0x1, "eor") 532 decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0") 533 decode_block += instCode(0x3, "rsb") 534 decode_block += adrCode(0x4, "add", add="(IntRegIndex)1") 535 decode_block += instCode(0x5, "adc") 536 decode_block += instCode(0x6, "sbc") 537 decode_block += instCode(0x7, "rsc") 538 decode_block += instCode(0x8, "tst", useDest = False) 539 decode_block += instCode(0x9, "teq", useDest = False) 540 decode_block += instCode(0xa, "cmp", useDest = False) 541 decode_block += instCode(0xb, "cmn", useDest = False) 542 decode_block += instCode(0xc, "orr") 543 decode_block += instCode(0xd, "mov", useOp1 = False) 544 decode_block += instCode(0xe, "bic") 545 decode_block += instCode(0xf, "mvn", useOp1 = False) 546 decode_block += ''' 547 default: 548 return new Unknown(machInst); 549 } 550 } 551 ''' 552}}; 553 554def format ArmSatAddSub() {{ 555 decode_block = ''' 556 { 557 IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 558 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 559 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 560 switch (OPCODE) { 561 case 0x8: 562 return new QaddRegCc(machInst, rd, rm, rn, 0, LSL); 563 case 0x9: 564 return new QsubRegCc(machInst, rd, rm, rn, 0, LSL); 565 case 0xa: 566 return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL); 567 case 0xb: 568 return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL); 569 default: 570 return new Unknown(machInst); 571 } 572 } 573 ''' 574}}; 575 576def format Thumb32DataProcReg() {{ 577 decode_block = ''' 578 { 579 const uint32_t op1 = bits(machInst, 23, 20); 580 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 581 const uint32_t op2 = bits(machInst, 7, 4); 582 if (bits(op1, 3) != 1) { 583 if (op2 == 0) { 584 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 585 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 586 switch (bits(op1, 2, 0)) { 587 case 0x0: 588 return new MovRegReg(machInst, rd, 589 INTREG_ZERO, rn, rm, LSL); 590 case 0x1: 591 return new MovRegRegCc(machInst, rd, 592 INTREG_ZERO, rn, rm, LSL); 593 case 0x2: 594 return new MovRegReg(machInst, rd, 595 INTREG_ZERO, rn, rm, LSR); 596 case 0x3: 597 return new MovRegRegCc(machInst, rd, 598 INTREG_ZERO, rn, rm, LSR); 599 case 0x4: 600 return new MovRegReg(machInst, rd, 601 INTREG_ZERO, rn, rm, ASR); 602 case 0x5: 603 return new MovRegRegCc(machInst, rd, 604 INTREG_ZERO, rn, rm, ASR); 605 case 0x6: 606 return new MovRegReg(machInst, rd, 607 INTREG_ZERO, rn, rm, ROR); 608 case 0x7: 609 return new MovRegRegCc(machInst, rd, 610 INTREG_ZERO, rn, rm, ROR); 611 } 612 } 613 { 614 const IntRegIndex rd = 615 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 616 const IntRegIndex rm = 617 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 618 const uint32_t rotation = 619 (uint32_t)bits(machInst, 5, 4) << 3; 620 switch (bits(op1, 2, 0)) { 621 case 0x0: 622 if (rn == 0xf) { 623 return new Sxth(machInst, rd, rotation, rm); 624 } else { 625 return new Sxtah(machInst, rd, rn, rm, rotation); 626 } 627 case 0x1: 628 if (rn == 0xf) { 629 return new Uxth(machInst, rd, rotation, rm); 630 } else { 631 return new Uxtah(machInst, rd, rn, rm, rotation); 632 } 633 case 0x2: 634 if (rn == 0xf) { 635 return new Sxtb16(machInst, rd, rotation, rm); 636 } else { 637 return new Sxtab16(machInst, rd, rn, rm, rotation); 638 } 639 case 0x3: 640 if (rn == 0xf) { 641 return new Uxtb16(machInst, rd, rotation, rm); 642 } else { 643 return new Uxtab16(machInst, rd, rn, rm, rotation); 644 } 645 case 0x4: 646 if (rn == 0xf) { 647 return new Sxtb(machInst, rd, rotation, rm); 648 } else { 649 return new Sxtab(machInst, rd, rn, rm, rotation); 650 } 651 case 0x5: 652 if (rn == 0xf) { 653 return new Uxtb(machInst, rd, rotation, rm); 654 } else { 655 return new Uxtab(machInst, rd, rn, rm, rotation); 656 } 657 default: 658 return new Unknown(machInst); 659 } 660 } 661 } else { 662 if (bits(op2, 3) == 0) { 663 const IntRegIndex rd = 664 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 665 const IntRegIndex rm = 666 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 667 if (bits(op2, 2) == 0x0) { 668 const uint32_t op1 = bits(machInst, 22, 20); 669 const uint32_t op2 = bits(machInst, 5, 4); 670 switch (op2) { 671 case 0x0: 672 switch (op1) { 673 case 0x1: 674 return new Sadd16RegCc(machInst, rd, 675 rn, rm, 0, LSL); 676 case 0x2: 677 return new SasxRegCc(machInst, rd, 678 rn, rm, 0, LSL); 679 case 0x6: 680 return new SsaxRegCc(machInst, rd, 681 rn, rm, 0, LSL); 682 case 0x5: 683 return new Ssub16RegCc(machInst, rd, 684 rn, rm, 0, LSL); 685 case 0x0: 686 return new Sadd8RegCc(machInst, rd, 687 rn, rm, 0, LSL); 688 case 0x4: 689 return new Ssub8RegCc(machInst, rd, 690 rn, rm, 0, LSL); 691 } 692 break; 693 case 0x1: 694 switch (op1) { 695 case 0x1: 696 return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL); 697 case 0x2: 698 return new QasxReg(machInst, rd, rn, rm, 0, LSL); 699 case 0x6: 700 return new QsaxReg(machInst, rd, rn, rm, 0, LSL); 701 case 0x5: 702 return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL); 703 case 0x0: 704 return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL); 705 case 0x4: 706 return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL); 707 } 708 break; 709 case 0x2: 710 switch (op1) { 711 case 0x1: 712 return new Shadd16Reg(machInst, rd, rn, rm, 0, LSL); 713 case 0x2: 714 return new ShasxReg(machInst, rd, rn, rm, 0, LSL); 715 case 0x6: 716 return new ShsaxReg(machInst, rd, rn, rm, 0, LSL); 717 case 0x5: 718 return new Shsub16Reg(machInst, rd, rn, rm, 0, LSL); 719 case 0x0: 720 return new Shadd8Reg(machInst, rd, rn, rm, 0, LSL); 721 case 0x4: 722 return new Shsub8Reg(machInst, rd, rn, rm, 0, LSL); 723 } 724 break; 725 } 726 } else { 727 const uint32_t op1 = bits(machInst, 22, 20); 728 const uint32_t op2 = bits(machInst, 5, 4); 729 switch (op2) { 730 case 0x0: 731 switch (op1) { 732 case 0x1: 733 return new Uadd16RegCc(machInst, rd, 734 rn, rm, 0, LSL); 735 case 0x2: 736 return new UasxRegCc(machInst, rd, 737 rn, rm, 0, LSL); 738 case 0x6: 739 return new UsaxRegCc(machInst, rd, 740 rn, rm, 0, LSL); 741 case 0x5: 742 return new Usub16RegCc(machInst, rd, 743 rn, rm, 0, LSL); 744 case 0x0: 745 return new Uadd8RegCc(machInst, rd, 746 rn, rm, 0, LSL); 747 case 0x4: 748 return new Usub8RegCc(machInst, rd, 749 rn, rm, 0, LSL); 750 } 751 break; 752 case 0x1: 753 switch (op1) { 754 case 0x1: 755 return new Uqadd16Reg(machInst, rd, rn, rm, 0, LSL); 756 case 0x2: 757 return new UqasxReg(machInst, rd, rn, rm, 0, LSL); 758 case 0x6: 759 return new UqsaxReg(machInst, rd, rn, rm, 0, LSL); 760 case 0x5: 761 return new Uqsub16Reg(machInst, rd, rn, rm, 0, LSL); 762 case 0x0: 763 return new Uqadd8Reg(machInst, rd, rn, rm, 0, LSL); 764 case 0x4: 765 return new Uqsub8Reg(machInst, rd, rn, rm, 0, LSL); 766 } 767 break; 768 case 0x2: 769 switch (op1) { 770 case 0x1: 771 return new Uhadd16Reg(machInst, rd, rn, rm, 0, LSL); 772 case 0x2: 773 return new UhasxReg(machInst, rd, rn, rm, 0, LSL); 774 case 0x6: 775 return new UhsaxReg(machInst, rd, rn, rm, 0, LSL); 776 case 0x5: 777 return new Uhsub16Reg(machInst, rd, rn, rm, 0, LSL); 778 case 0x0: 779 return new Uhadd8Reg(machInst, rd, rn, rm, 0, LSL); 780 case 0x4: 781 return new Uhsub8Reg(machInst, rd, rn, rm, 0, LSL); 782 } 783 break; 784 } 785 } 786 } else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) { 787 const uint32_t op1 = bits(machInst, 21, 20); 788 const uint32_t op2 = bits(machInst, 5, 4); 789 const IntRegIndex rd = 790 (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 791 const IntRegIndex rm = 792 (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 793 switch (op1) { 794 case 0x0: 795 switch (op2) { 796 case 0x0: 797 return new QaddRegCc(machInst, rd, 798 rm, rn, 0, LSL); 799 case 0x1: 800 return new QdaddRegCc(machInst, rd, 801 rm, rn, 0, LSL); 802 case 0x2: 803 return new QsubRegCc(machInst, rd, 804 rm, rn, 0, LSL); 805 case 0x3: 806 return new QdsubRegCc(machInst, rd, 807 rm, rn, 0, LSL); 808 } 809 break; 810 case 0x1: 811 switch (op2) { 812 case 0x0: 813 return new Rev(machInst, rd, rn); 814 case 0x1: 815 return new Rev16(machInst, rd, rn); 816 case 0x2: 817 return new Rbit(machInst, rd, rm); 818 case 0x3: 819 return new Revsh(machInst, rd, rn); 820 } 821 break; 822 case 0x2: 823 if (op2 == 0) { 824 return new Sel(machInst, rd, rn, rm); 825 } 826 break; 827 case 0x3: 828 if (op2 == 0) { 829 return new Clz(machInst, rd, rm); 830 } 831 } 832 } 833 return new Unknown(machInst); 834 } 835 } 836 ''' 837}}; 838 839def format Thumb16ShiftAddSubMoveCmp() {{ 840 decode_block = ''' 841 { 842 const uint32_t imm5 = bits(machInst, 10, 6); 843 const uint32_t imm3 = bits(machInst, 8, 6); 844 const uint32_t imm8 = bits(machInst, 7, 0); 845 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 846 const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 847 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 848 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6); 849 switch (bits(machInst, 13, 11)) { 850 case 0x0: // lsl 851 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL); 852 case 0x1: // lsr 853 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR); 854 case 0x2: // asr 855 return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR); 856 case 0x3: 857 switch (bits(machInst, 10, 9)) { 858 case 0x0: 859 return new AddRegCc(machInst, rd, rn, rm, 0, LSL); 860 case 0x1: 861 return new SubRegCc(machInst, rd, rn, rm, 0, LSL); 862 case 0x2: 863 return new AddImmCc(machInst, rd, rn, imm3, true); 864 case 0x3: 865 return new SubImmCc(machInst, rd, rn, imm3, true); 866 } 867 case 0x4: 868 return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false); 869 case 0x5: 870 return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true); 871 case 0x6: 872 return new AddImmCc(machInst, rd8, rd8, imm8, true); 873 case 0x7: 874 return new SubImmCc(machInst, rd8, rd8, imm8, true); 875 } 876 } 877 ''' 878}}; 879 880def format Thumb16DataProcessing() {{ 881 decode_block = ''' 882 { 883 const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 884 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 885 switch (bits(machInst, 9, 6)) { 886 case 0x0: 887 return new AndRegCc(machInst, rdn, rdn, rm, 0, LSL); 888 case 0x1: 889 return new EorRegCc(machInst, rdn, rdn, rm, 0, LSL); 890 case 0x2: //lsl 891 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSL); 892 case 0x3: //lsr 893 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, LSR); 894 case 0x4: //asr 895 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ASR); 896 case 0x5: 897 return new AdcRegCc(machInst, rdn, rdn, rm, 0, LSL); 898 case 0x6: 899 return new SbcRegCc(machInst, rdn, rdn, rm, 0, LSL); 900 case 0x7: // ror 901 return new MovRegRegCc(machInst, rdn, INTREG_ZERO, rdn, rm, ROR); 902 case 0x8: 903 return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 904 case 0x9: 905 return new RsbImmCc(machInst, rdn, rm, 0, true); 906 case 0xa: 907 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 908 case 0xb: 909 return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 910 case 0xc: 911 return new OrrRegCc(machInst, rdn, rdn, rm, 0, LSL); 912 case 0xd: 913 return new MulCc(machInst, rdn, rm, rdn); 914 case 0xe: 915 return new BicRegCc(machInst, rdn, rdn, rm, 0, LSL); 916 case 0xf: 917 return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 918 } 919 } 920 ''' 921}}; 922 923def format Thumb16SpecDataAndBx() {{ 924 decode_block = ''' 925 { 926 const IntRegIndex rdn = 927 (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) | 928 (bits(machInst, 7) << 3)); 929 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3); 930 switch (bits(machInst, 9, 8)) { 931 case 0x0: 932 return new AddReg(machInst, rdn, rdn, rm, 0, LSL); 933 case 0x1: 934 return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL); 935 case 0x2: 936 return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL); 937 case 0x3: 938 if (bits(machInst, 7) == 0) { 939 return new BxReg(machInst, 940 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 941 COND_UC); 942 } else { 943 return new BlxReg(machInst, 944 (IntRegIndex)(uint32_t)bits(machInst, 6, 3), 945 COND_UC); 946 } 947 } 948 } 949 ''' 950}}; 951 952def format Thumb16Adr() {{ 953 decode_block = ''' 954 { 955 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 956 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 957 return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false); 958 } 959 ''' 960}}; 961 962def format Thumb16AddSp() {{ 963 decode_block = ''' 964 { 965 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8); 966 const uint32_t imm8 = bits(machInst, 7, 0) << 2; 967 return new AddImm(machInst, rd, INTREG_SP, imm8, true); 968 } 969 ''' 970}}; 971 972def format Thumb16Misc() {{ 973 decode_block = ''' 974 { 975 switch (bits(machInst, 11, 8)) { 976 case 0x0: 977 if (bits(machInst, 7)) { 978 return new SubImm(machInst, INTREG_SP, INTREG_SP, 979 bits(machInst, 6, 0) << 2, true); 980 } else { 981 return new AddImm(machInst, INTREG_SP, INTREG_SP, 982 bits(machInst, 6, 0) << 2, true); 983 } 984 case 0x1: 985 return new Cbz(machInst, 986 (bits(machInst, 9) << 6) | 987 (bits(machInst, 7, 3) << 1), 988 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 989 case 0x2: 990 { 991 const IntRegIndex rd = 992 (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 993 const IntRegIndex rm = 994 (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 995 switch (bits(machInst, 7, 6)) { 996 case 0x0: 997 return new Sxth(machInst, rd, 0, rm); 998 case 0x1: 999 return new Sxtb(machInst, rd, 0, rm); 1000 case 0x2: 1001 return new Uxth(machInst, rd, 0, rm); 1002 case 0x3: 1003 return new Uxtb(machInst, rd, 0, rm); 1004 } 1005 } 1006 case 0x3: 1007 return new Cbz(machInst, 1008 (bits(machInst, 9) << 6) | 1009 (bits(machInst, 7, 3) << 1), 1010 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1011 case 0x4: 1012 case 0x5: 1013 { 1014 const uint32_t m = bits(machInst, 8); 1015 const uint32_t regList = bits(machInst, 7, 0) | (m << 14); 1016 return new LdmStm(machInst, INTREG_SP, false, false, false, 1017 true, false, regList); 1018 } 1019 case 0x6: 1020 { 1021 const uint32_t opBits = bits(machInst, 7, 5); 1022 if (opBits == 2) { 1023 return new WarnUnimplemented("setend", machInst); 1024 } else if (opBits == 3) { 1025 return new WarnUnimplemented("cps", machInst); 1026 } 1027 } 1028 case 0x9: 1029 return new Cbnz(machInst, 1030 (bits(machInst, 9) << 6) | 1031 (bits(machInst, 7, 3) << 1), 1032 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1033 case 0xa: 1034 { 1035 IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0); 1036 IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3); 1037 switch (bits(machInst, 7, 6)) { 1038 case 0x0: 1039 return new Rev(machInst, rd, rm); 1040 case 0x1: 1041 return new Rev16(machInst, rd, rm); 1042 case 0x3: 1043 return new Revsh(machInst, rd, rm); 1044 default: 1045 break; 1046 } 1047 } 1048 break; 1049 case 0xb: 1050 return new Cbnz(machInst, 1051 (bits(machInst, 9) << 6) | 1052 (bits(machInst, 7, 3) << 1), 1053 (IntRegIndex)(uint32_t)bits(machInst, 2, 0)); 1054 case 0xc: 1055 case 0xd: 1056 { 1057 const uint32_t p = bits(machInst, 8); 1058 const uint32_t regList = bits(machInst, 7, 0) | (p << 15); 1059 return new LdmStm(machInst, INTREG_SP, true, true, false, 1060 true, true, regList); 1061 } 1062 case 0xe: 1063 return new WarnUnimplemented("bkpt", machInst); 1064 case 0xf: 1065 if (bits(machInst, 3, 0) != 0) 1066 return new WarnUnimplemented("it", machInst); 1067 switch (bits(machInst, 7, 4)) { 1068 case 0x0: 1069 return new NopInst(machInst); 1070 case 0x1: 1071 return new WarnUnimplemented("yield", machInst); 1072 case 0x2: 1073 return new WarnUnimplemented("wfe", machInst); 1074 case 0x3: 1075 return new WarnUnimplemented("wfi", machInst); 1076 case 0x4: 1077 return new WarnUnimplemented("sev", machInst); 1078 default: 1079 return new WarnUnimplemented("unallocated_hint", machInst); 1080 } 1081 default: 1082 break; 1083 } 1084 return new Unknown(machInst); 1085 } 1086 ''' 1087}}; 1088 1089def format Thumb32DataProcModImm() {{ 1090 1091 def decInst(mnem, dest="rd", op1="rn"): 1092 return ''' 1093 if (s) { 1094 return new %(mnem)sImmCc(machInst, %(dest)s, 1095 %(op1)s, imm, rotC); 1096 } else { 1097 return new %(mnem)sImm(machInst, %(dest)s, 1098 %(op1)s, imm, rotC); 1099 } 1100 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 1101 1102 decode_block = ''' 1103 { 1104 const uint32_t op = bits(machInst, 24, 21); 1105 const bool s = (bits(machInst, 20) == 1); 1106 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1107 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1108 const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 | 1109 bits(machInst, 14, 12); 1110 const bool rotC = ctrlImm > 3; 1111 const uint32_t dataImm = bits(machInst, 7, 0); 1112 const uint32_t imm = modified_imm(ctrlImm, dataImm); 1113 switch (op) { 1114 case 0x0: 1115 if (rd == INTREG_PC) { 1116 %(tst)s 1117 } else { 1118 %(and)s 1119 } 1120 case 0x1: 1121 %(bic)s 1122 case 0x2: 1123 if (rn == INTREG_PC) { 1124 %(mov)s 1125 } else { 1126 %(orr)s 1127 } 1128 case 0x3: 1129 if (rn == INTREG_PC) { 1130 %(mvn)s 1131 } else { 1132 %(orn)s 1133 } 1134 case 0x4: 1135 if (rd == INTREG_PC) { 1136 %(teq)s 1137 } else { 1138 %(eor)s 1139 } 1140 case 0x8: 1141 if (rd == INTREG_PC) { 1142 %(cmn)s 1143 } else { 1144 %(add)s 1145 } 1146 case 0xa: 1147 %(adc)s 1148 case 0xb: 1149 %(sbc)s 1150 case 0xd: 1151 if (rd == INTREG_PC) { 1152 %(cmp)s 1153 } else { 1154 %(sub)s 1155 } 1156 case 0xe: 1157 %(rsb)s 1158 default: 1159 return new Unknown(machInst); 1160 } 1161 } 1162 ''' % { 1163 "tst" : decInst("Tst", "INTREG_ZERO"), 1164 "and" : decInst("And"), 1165 "bic" : decInst("Bic"), 1166 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1167 "orr" : decInst("Orr"), 1168 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1169 "orn" : decInst("Orn"), 1170 "teq" : decInst("Teq", dest="INTREG_ZERO"), 1171 "eor" : decInst("Eor"), 1172 "cmn" : decInst("Cmn", dest="INTREG_ZERO"), 1173 "add" : decInst("Add"), 1174 "adc" : decInst("Adc"), 1175 "sbc" : decInst("Sbc"), 1176 "cmp" : decInst("Cmp", dest="INTREG_ZERO"), 1177 "sub" : decInst("Sub"), 1178 "rsb" : decInst("Rsb") 1179 } 1180}}; 1181 1182def format Thumb32DataProcPlainBin() {{ 1183 decode_block = ''' 1184 { 1185 const uint32_t op = bits(machInst, 24, 20); 1186 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1187 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1188 switch (op) { 1189 case 0x0: 1190 { 1191 const uint32_t imm = bits(machInst, 7, 0) | 1192 (bits(machInst, 14, 12) << 8) | 1193 (bits(machInst, 26) << 11); 1194 if (rn == 0xf) { 1195 return new AdrImm(machInst, rd, (IntRegIndex)1, 1196 imm, false); 1197 } else { 1198 return new AddImm(machInst, rd, rn, imm, true); 1199 } 1200 } 1201 case 0x4: 1202 { 1203 const uint32_t imm = bits(machInst, 7, 0) | 1204 (bits(machInst, 14, 12) << 8) | 1205 (bits(machInst, 26) << 11) | 1206 (bits(machInst, 19, 16) << 12); 1207 return new MovImm(machInst, rd, INTREG_ZERO, imm, true); 1208 } 1209 case 0xa: 1210 { 1211 const uint32_t imm = bits(machInst, 7, 0) | 1212 (bits(machInst, 14, 12) << 8) | 1213 (bits(machInst, 26) << 11); 1214 if (rn == 0xf) { 1215 return new AdrImm(machInst, rd, (IntRegIndex)0, 1216 imm, false); 1217 } else { 1218 return new SubImm(machInst, rd, rn, imm, true); 1219 } 1220 } 1221 case 0xc: 1222 { 1223 const uint32_t imm = bits(machInst, 7, 0) | 1224 (bits(machInst, 14, 12) << 8) | 1225 (bits(machInst, 26) << 11) | 1226 (bits(machInst, 19, 16) << 12); 1227 return new MovtImm(machInst, rd, rd, imm, true); 1228 } 1229 case 0x12: 1230 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1231 const uint32_t satImm = bits(machInst, 4, 0); 1232 return new Ssat16(machInst, rd, satImm + 1, rn); 1233 } 1234 // Fall through on purpose... 1235 case 0x10: 1236 { 1237 const uint32_t satImm = bits(machInst, 4, 0); 1238 const uint32_t imm = bits(machInst, 7, 6) | 1239 (bits(machInst, 14, 12) << 2); 1240 const ArmShiftType type = 1241 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1242 return new Ssat(machInst, rd, satImm + 1, rn, imm, type); 1243 } 1244 case 0x14: 1245 { 1246 const uint32_t lsb = bits(machInst, 7, 6) | 1247 (bits(machInst, 14, 12) << 2); 1248 const uint32_t msb = lsb + bits(machInst, 4, 0); 1249 return new Sbfx(machInst, rd, rn, lsb, msb); 1250 } 1251 case 0x16: 1252 { 1253 const uint32_t lsb = bits(machInst, 7, 6) | 1254 (bits(machInst, 14, 12) << 2); 1255 const uint32_t msb = bits(machInst, 4, 0); 1256 if (rn == 0xf) { 1257 return new Bfc(machInst, rd, rd, lsb, msb); 1258 } else { 1259 return new Bfi(machInst, rd, rn, lsb, msb); 1260 } 1261 } 1262 case 0x1a: 1263 if (!(bits(machInst, 14, 12) || bits(machInst, 7, 6))) { 1264 const uint32_t satImm = bits(machInst, 4, 0); 1265 return new Usat16(machInst, rd, satImm, rn); 1266 } 1267 // Fall through on purpose... 1268 case 0x18: 1269 { 1270 const uint32_t satImm = bits(machInst, 4, 0); 1271 const uint32_t imm = bits(machInst, 7, 6) | 1272 (bits(machInst, 14, 12) << 2); 1273 const ArmShiftType type = 1274 (ArmShiftType)(uint32_t)bits(machInst, 21, 20); 1275 return new Usat(machInst, rd, satImm, rn, imm, type); 1276 } 1277 case 0x1c: 1278 { 1279 const uint32_t lsb = bits(machInst, 7, 6) | 1280 (bits(machInst, 14, 12) << 2); 1281 const uint32_t msb = lsb + bits(machInst, 4, 0); 1282 return new Ubfx(machInst, rd, rn, lsb, msb); 1283 } 1284 default: 1285 return new Unknown(machInst); 1286 } 1287 } 1288 ''' 1289}}; 1290 1291def format Thumb32DataProcShiftReg() {{ 1292 1293 def decInst(mnem, dest="rd", op1="rn"): 1294 return ''' 1295 if (s) { 1296 return new %(mnem)sRegCc(machInst, %(dest)s, 1297 %(op1)s, rm, amt, type); 1298 } else { 1299 return new %(mnem)sReg(machInst, %(dest)s, 1300 %(op1)s, rm, amt, type); 1301 } 1302 ''' % {"mnem" : mnem, "dest" : dest, "op1" : op1} 1303 1304 decode_block = ''' 1305 { 1306 const uint32_t op = bits(machInst, 24, 21); 1307 const bool s = (bits(machInst, 20) == 1); 1308 const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1309 const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 1310 const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 1311 const uint32_t amt = (bits(machInst, 14, 12) << 2) | 1312 bits(machInst, 7, 6); 1313 const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4); 1314 switch (op) { 1315 case 0x0: 1316 if (rd == INTREG_PC) { 1317 %(tst)s 1318 } else { 1319 %(and)s 1320 } 1321 case 0x1: 1322 %(bic)s 1323 case 0x2: 1324 if (rn == INTREG_PC) { 1325 %(mov)s 1326 } else { 1327 %(orr)s 1328 } 1329 case 0x3: 1330 if (rn == INTREG_PC) { 1331 %(mvn)s 1332 } else { 1333 %(orn)s 1334 } 1335 case 0x4: 1336 if (rd == INTREG_PC) { 1337 %(teq)s 1338 } else { 1339 %(eor)s 1340 } 1341 case 0x6: 1342 if (type) { 1343 return new PkhtbReg(machInst, rd, rn, rm, amt, type); 1344 } else { 1345 return new PkhbtReg(machInst, rd, rn, rm, amt, type); 1346 } 1347 case 0x8: 1348 if (rd == INTREG_PC) { 1349 %(cmn)s 1350 } else { 1351 %(add)s 1352 } 1353 case 0xa: 1354 %(adc)s 1355 case 0xb: 1356 %(sbc)s 1357 case 0xd: 1358 if (rd == INTREG_PC) { 1359 %(cmp)s 1360 } else { 1361 %(sub)s 1362 } 1363 case 0xe: 1364 %(rsb)s 1365 default: 1366 return new Unknown(machInst); 1367 } 1368 } 1369 ''' % { 1370 "tst" : decInst("Tst", "INTREG_ZERO"), 1371 "and" : decInst("And"), 1372 "bic" : decInst("Bic"), 1373 "mov" : decInst("Mov", op1="INTREG_ZERO"), 1374 "orr" : decInst("Orr"), 1375 "mvn" : decInst("Mvn", op1="INTREG_ZERO"), 1376 "orn" : decInst("Orn"), 1377 "teq" : decInst("Teq", "INTREG_ZERO"), 1378 "eor" : decInst("Eor"), 1379 "cmn" : decInst("Cmn", "INTREG_ZERO"), 1380 "add" : decInst("Add"), 1381 "adc" : decInst("Adc"), 1382 "sbc" : decInst("Sbc"), 1383 "cmp" : decInst("Cmp", "INTREG_ZERO"), 1384 "sub" : decInst("Sub"), 1385 "rsb" : decInst("Rsb") 1386 } 1387}}; 1388