x86: Use operand size 4 when it would be 2 for cmpxchg8b.

This means the instruction is treated as cmpxchg8b when the effective
operand size is 16 bits.

Change-Id: I4d9bb295f96097e1746a9bbccb2c579d14738fab
Reviewed-on: https://gem5-review.googlesource.com/6603
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: implements emms instruction

x86: implement x87 fp instruction fnstsw
This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.

copyright: Change HP copyright on x86 code to be more friendly

X86: Add a common named flag for signed media operations.

X86: Create a common flag with a name to indicate high multiplies.

X86: Create a common flag with a name to indicate scalar media instructions.

X86: Add microassembler symbols for floating point stack register operands.

X86: Add microcode assembler symbols for mmx registers.

X86: Let microops force folding an index into the high byte of a register.

X86: Take limitted advantage of the compilers type checking for microop operands.

X86: Add segmentation checks for ldt related descriptors and selectors.

X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.

X86: Make the microcode assembler recognize r8-r15.

X86: Add a check to chks to verify a task state segment descriptor.

X86: Add a check to chks which raises #GP(selector) if selector is NULL or not in the GDT.

X86: Distinguish between hardware and software interrupts/exceptions

X86: Fix the upper bound on some ranges that were setting up the micro code assembler.

X86: Add wrval/rdval microops for reading significant miscregs.

X86: Implement local labels for the ROM that actually refer into the ROM.

X86: Add a check type for interrupt gates.

X86: Let the microassembler know about the microcode only H segment.

X86: Create a handy way to access labels from the ROM in microcode.

X86: Make X86's microcode ROM actually do something.

X86: Change what the microop chks does.
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.

X86: Add microops and supporting code to manipulate the whole rflags register.

X86: Redo the bit test instructions.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the lgdt instruction.

X86: Implement the wrcr microop which writes a control register, and some control register work.

X86: Various fixes to indexing segmentation related registers

X86: Implement the in/out instructions. These will still need support from the TLB and memory system.

X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.

X86: Fix x87 floating point stack register indexing.

X86: Put in the foundation for x87 stack based fp registers.

X86: Add floating point micro registers.

X86: Implement the movlpd instruction.

X86: Make cpuid actually consider the eax parameter and return different values.

X86: Implemented and hooked in SCAS (scan string)
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.

X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

Add symbols for each of the flags a microop could set and each condition it could check.

Pull some hard coded base classes out of the isa description.

Make symbols for regular registers.

Define symbols for the x86 specialization of the microassembler.

Comment out some unnecessary debug output.

Adjust a few more comments.

Clean up where files are included, and get rid of some cruft.

src/arch/x86/isa/main.isa:
Clean up where files are included.

Big changes to use the new microcode assembler.

Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system

Reworked x86 a bit

Accidentally didn't save when moving the specialization code out of here.

Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa

Consolidated the microcode assembler to help separate it from more x86-centric stuff.

Refactored the x86 isa description some more. There should be more seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere.

The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.

1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
Implemented polymorphic microops and changed around the microcode assembler syntax.

Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:

MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.

A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.

Add a microcode assembler. A microcode "program" is a series of statements. Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself.