microasm.isa revision 6517:584314d07394
110515SAli.Saidi@ARM.com// -*- mode:c++ -*- 210515SAli.Saidi@ARM.com 310852Sandreas.hansson@arm.com// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 410852Sandreas.hansson@arm.com// All rights reserved. 510852Sandreas.hansson@arm.com// 610515SAli.Saidi@ARM.com// Redistribution and use of this software in source and binary forms, 710852Sandreas.hansson@arm.com// with or without modification, are permitted provided that the 810852Sandreas.hansson@arm.com// following conditions are met: 910852Sandreas.hansson@arm.com// 1010852Sandreas.hansson@arm.com// The software must be used only for Non-Commercial Use which means any 1110852Sandreas.hansson@arm.com// use which is NOT directed to receiving any direct monetary 1210852Sandreas.hansson@arm.com// compensation for, or commercial advantage from such use. Illustrative 1310852Sandreas.hansson@arm.com// examples of non-commercial use are academic research, personal study, 1410515SAli.Saidi@ARM.com// teaching, education and corporate research & development. 1510515SAli.Saidi@ARM.com// Illustrative examples of commercial use are distributing products for 1610852Sandreas.hansson@arm.com// commercial advantage and providing services using the software for 1710852Sandreas.hansson@arm.com// commercial advantage. 1810852Sandreas.hansson@arm.com// 1910852Sandreas.hansson@arm.com// If you wish to use this software or functionality therein that may be 2010852Sandreas.hansson@arm.com// covered by patents for commercial use, please contact: 2110852Sandreas.hansson@arm.com// Director of Intellectual Property Licensing 2210852Sandreas.hansson@arm.com// Office of Strategy and Technology 2310852Sandreas.hansson@arm.com// Hewlett-Packard Company 2410852Sandreas.hansson@arm.com// 1501 Page Mill Road 2510636Snilay@cs.wisc.edu// Palo Alto, California 94304 2610852Sandreas.hansson@arm.com// 2710852Sandreas.hansson@arm.com// Redistributions of source code must retain the above copyright notice, 2810852Sandreas.hansson@arm.com// this list of conditions and the following disclaimer. Redistributions 2910852Sandreas.hansson@arm.com// in binary form must reproduce the above copyright notice, this list of 3010852Sandreas.hansson@arm.com// conditions and the following disclaimer in the documentation and/or 3110852Sandreas.hansson@arm.com// other materials provided with the distribution. Neither the name of 3210852Sandreas.hansson@arm.com// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 3310852Sandreas.hansson@arm.com// contributors may be used to endorse or promote products derived from 3410636Snilay@cs.wisc.edu// this software without specific prior written permission. No right of 3510852Sandreas.hansson@arm.com// sublicense is granted herewith. Derivatives of the software and 3610852Sandreas.hansson@arm.com// output created using the software may be prepared, but only for 3710852Sandreas.hansson@arm.com// Non-Commercial Uses. Derivatives of the software may be shared with 3810852Sandreas.hansson@arm.com// others provided: (i) the others agree to abide by the list of 3910852Sandreas.hansson@arm.com// conditions herein which includes the Non-Commercial Use restrictions; 4010852Sandreas.hansson@arm.com// and (ii) such Derivatives of the software include the above copyright 4110852Sandreas.hansson@arm.com// notice to acknowledge the contribution from this software where 4210852Sandreas.hansson@arm.com// applicable, this list of conditions and the disclaimer below. 4310852Sandreas.hansson@arm.com// 4410852Sandreas.hansson@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 4510753Sstever@gmail.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 4610852Sandreas.hansson@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 4710852Sandreas.hansson@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 4810852Sandreas.hansson@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4910852Sandreas.hansson@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 5010852Sandreas.hansson@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5110852Sandreas.hansson@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5210852Sandreas.hansson@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5310852Sandreas.hansson@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 5410852Sandreas.hansson@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5510852Sandreas.hansson@arm.com// 5610852Sandreas.hansson@arm.com// Authors: Gabe Black 5710852Sandreas.hansson@arm.com 5810852Sandreas.hansson@arm.com//Include the definitions of the micro ops. 5910852Sandreas.hansson@arm.com//These are python representations of static insts which stand on their own 6010852Sandreas.hansson@arm.com//and make up an internal instruction set. They are used by the micro 6110852Sandreas.hansson@arm.com//assembler. 6210852Sandreas.hansson@arm.com##include "microops/microops.isa" 6310852Sandreas.hansson@arm.com 6410852Sandreas.hansson@arm.com//Include code to build macroops in both C++ and python. 6510852Sandreas.hansson@arm.com##include "macroop.isa" 6610852Sandreas.hansson@arm.com 6710852Sandreas.hansson@arm.com//Include code to fill out the microcode ROM in both C++ and python. 6810852Sandreas.hansson@arm.com##include "rom.isa" 6910852Sandreas.hansson@arm.com 7010852Sandreas.hansson@arm.comlet {{ 7110852Sandreas.hansson@arm.com import sys 7210852Sandreas.hansson@arm.com sys.path[0:0] = ["src/arch/x86/isa/"] 7310852Sandreas.hansson@arm.com from insts import microcode 7410852Sandreas.hansson@arm.com # print microcode 7510852Sandreas.hansson@arm.com from micro_asm import MicroAssembler, Rom_Macroop 7610852Sandreas.hansson@arm.com mainRom = X86MicrocodeRom('main ROM') 7710852Sandreas.hansson@arm.com assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop) 7810852Sandreas.hansson@arm.com 7910852Sandreas.hansson@arm.com def regIdx(idx): 8010852Sandreas.hansson@arm.com return "InstRegIndex(%s)" % idx 8110852Sandreas.hansson@arm.com 8210852Sandreas.hansson@arm.com assembler.symbols["regIdx"] = regIdx 8310852Sandreas.hansson@arm.com 8410852Sandreas.hansson@arm.com # Add in symbols for the microcode registers 8510852Sandreas.hansson@arm.com for num in range(16): 8610852Sandreas.hansson@arm.com assembler.symbols["t%d" % num] = regIdx("NUM_INTREGS+%d" % num) 8710852Sandreas.hansson@arm.com for num in range(8): 8810852Sandreas.hansson@arm.com assembler.symbols["ufp%d" % num] = \ 8910852Sandreas.hansson@arm.com regIdx("FLOATREG_MICROFP(%d)" % num) 9010852Sandreas.hansson@arm.com # Add in symbols for the segment descriptor registers 9110852Sandreas.hansson@arm.com for letter in ("C", "D", "E", "F", "G", "H", "S"): 9210852Sandreas.hansson@arm.com assembler.symbols["%ss" % letter.lower()] = \ 9310852Sandreas.hansson@arm.com regIdx("SEGMENT_REG_%sS" % letter) 9410852Sandreas.hansson@arm.com 9510852Sandreas.hansson@arm.com # Add in symbols for the various checks of segment selectors. 9610852Sandreas.hansson@arm.com for check in ("NoCheck", "CSCheck", "CallGateCheck", "IntGateCheck", 9710852Sandreas.hansson@arm.com "SoftIntGateCheck", "SSCheck", "IretCheck", "IntCSCheck", 9810515SAli.Saidi@ARM.com "TRCheck", "TSSCheck", "InGDTCheck", "LDTCheck"): 9910852Sandreas.hansson@arm.com assembler.symbols[check] = "Seg%s" % check 10010852Sandreas.hansson@arm.com 10110515SAli.Saidi@ARM.com for reg in ("TR", "IDTR"): 10210515SAli.Saidi@ARM.com assembler.symbols[reg.lower()] = regIdx("SYS_SEGMENT_REG_%s" % reg) 10310515SAli.Saidi@ARM.com 10410515SAli.Saidi@ARM.com for reg in ("TSL", "TSG"): 10510515SAli.Saidi@ARM.com assembler.symbols[reg.lower()] = regIdx("SEGMENT_REG_%s" % reg) 10610515SAli.Saidi@ARM.com 10710852Sandreas.hansson@arm.com # Miscellaneous symbols 10810515SAli.Saidi@ARM.com symbols = { 10910515SAli.Saidi@ARM.com "reg" : regIdx("env.reg"), 11010515SAli.Saidi@ARM.com "xmml" : regIdx("FLOATREG_XMM_LOW(env.reg)"), 11110515SAli.Saidi@ARM.com "xmmh" : regIdx("FLOATREG_XMM_HIGH(env.reg)"), 11210515SAli.Saidi@ARM.com "regm" : regIdx("env.regm"), 11310515SAli.Saidi@ARM.com "xmmlm" : regIdx("FLOATREG_XMM_LOW(env.regm)"), 11410852Sandreas.hansson@arm.com "xmmhm" : regIdx("FLOATREG_XMM_HIGH(env.regm)"), 11510852Sandreas.hansson@arm.com "mmx" : regIdx("FLOATREG_MMX(env.reg)"), 11610852Sandreas.hansson@arm.com "mmxm" : regIdx("FLOATREG_MMX(env.regm)"), 11710852Sandreas.hansson@arm.com "imm" : "adjustedImm", 11810852Sandreas.hansson@arm.com "disp" : "adjustedDisp", 11910852Sandreas.hansson@arm.com "seg" : regIdx("env.seg"), 12010852Sandreas.hansson@arm.com "scale" : "env.scale", 12110852Sandreas.hansson@arm.com "index" : regIdx("env.index"), 12210852Sandreas.hansson@arm.com "base" : regIdx("env.base"), 12310852Sandreas.hansson@arm.com "dsz" : "env.dataSize", 12410852Sandreas.hansson@arm.com "asz" : "env.addressSize", 12510852Sandreas.hansson@arm.com "ssz" : "env.stackSize" 12610726Sandreas.hansson@arm.com } 12710753Sstever@gmail.com assembler.symbols.update(symbols) 12810852Sandreas.hansson@arm.com 12910852Sandreas.hansson@arm.com assembler.symbols["ldsz"] = \ 13010753Sstever@gmail.com "((env.dataSize == 8) ? 3 : (env.dataSize == 4) ? 2 : 1)" 13110852Sandreas.hansson@arm.com 13210852Sandreas.hansson@arm.com assembler.symbols["lasz"] = \ 13310852Sandreas.hansson@arm.com "((env.addressSize == 8) ? 3 : (env.addressSize == 4) ? 2 : 1)" 13410852Sandreas.hansson@arm.com 13510852Sandreas.hansson@arm.com assembler.symbols["lssz"] = \ 13610726Sandreas.hansson@arm.com "((env.stackSize == 8) ? 3 : (env.stackSize == 4) ? 2 : 1)" 13710515SAli.Saidi@ARM.com 13810515SAli.Saidi@ARM.com # Short hand for common scale-index-base combinations. 13910515SAli.Saidi@ARM.com assembler.symbols["sib"] = \ 14010515SAli.Saidi@ARM.com [symbols["scale"], symbols["index"], symbols["base"]] 14110515SAli.Saidi@ARM.com assembler.symbols["riprel"] = \ 14210515SAli.Saidi@ARM.com ["1", assembler.symbols["t0"], assembler.symbols["t7"]] 14310515SAli.Saidi@ARM.com 14410515SAli.Saidi@ARM.com # This segment selects an internal address space mapped to MSRs, 14510515SAli.Saidi@ARM.com # CPUID info, etc. 14610515SAli.Saidi@ARM.com assembler.symbols["intseg"] = regIdx("SEGMENT_REG_MS") 14710515SAli.Saidi@ARM.com # This segment always has base 0, and doesn't imply any special handling 14810515SAli.Saidi@ARM.com # like the internal segment above 14910515SAli.Saidi@ARM.com assembler.symbols["flatseg"] = regIdx("SEGMENT_REG_LS") 15010515SAli.Saidi@ARM.com 15110515SAli.Saidi@ARM.com for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di', \ 15210515SAli.Saidi@ARM.com '8', '9', '10', '11', '12', '13', '14', '15'): 15310515SAli.Saidi@ARM.com assembler.symbols["r%s" % reg] = \ 15410515SAli.Saidi@ARM.com regIdx("INTREG_R%s" % reg.upper()) 15510515SAli.Saidi@ARM.com 15610515SAli.Saidi@ARM.com for reg in ('ah', 'bh', 'ch', 'dh'): 15710515SAli.Saidi@ARM.com assembler.symbols[reg] = \ 15810515SAli.Saidi@ARM.com regIdx("INTREG_FOLDED(INTREG_%s, IntFoldBit)" % reg.upper()) 15910515SAli.Saidi@ARM.com 16010515SAli.Saidi@ARM.com for reg in range(16): 16110515SAli.Saidi@ARM.com assembler.symbols["cr%d" % reg] = regIdx("MISCREG_CR%d" % reg) 16210852Sandreas.hansson@arm.com 16310852Sandreas.hansson@arm.com for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF', \ 16410852Sandreas.hansson@arm.com 'TF', 'IF', 'NT', 'RF', 'VM', 'AC', 'VIF', 'VIP', 'ID'): 16510852Sandreas.hansson@arm.com assembler.symbols[flag] = flag + "Bit" 16610852Sandreas.hansson@arm.com 16710852Sandreas.hansson@arm.com for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF', 16810852Sandreas.hansson@arm.com 'MSTRZ', 'STRZ', 'MSTRC', 16910852Sandreas.hansson@arm.com 'OF', 'CF', 'ZF', 'CvZF', 17010852Sandreas.hansson@arm.com 'SF', 'PF', 'SxOF', 'SxOvZF'): 17110852Sandreas.hansson@arm.com assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond 17210852Sandreas.hansson@arm.com assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond 17310852Sandreas.hansson@arm.com assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF" 17410852Sandreas.hansson@arm.com assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF" 17510852Sandreas.hansson@arm.com 17610852Sandreas.hansson@arm.com assembler.symbols["CTrue"] = "ConditionTests::True" 17710852Sandreas.hansson@arm.com assembler.symbols["CFalse"] = "ConditionTests::False" 17810852Sandreas.hansson@arm.com 17910852Sandreas.hansson@arm.com for reg in ('sysenter_cs', 'sysenter_esp', 'sysenter_eip', 18010852Sandreas.hansson@arm.com 'star', 'lstar', 'cstar', 'sf_mask', 18110852Sandreas.hansson@arm.com 'kernel_gs_base'): 18210852Sandreas.hansson@arm.com assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper()) 18310852Sandreas.hansson@arm.com 18410852Sandreas.hansson@arm.com # Code literal which forces a default 64 bit operand size in 64 bit mode. 18510852Sandreas.hansson@arm.com assembler.symbols["oszIn64Override"] = ''' 18610852Sandreas.hansson@arm.com if (machInst.mode.submode == SixtyFourBitMode && 18710852Sandreas.hansson@arm.com env.dataSize == 4) 18810852Sandreas.hansson@arm.com env.dataSize = 8; 18910852Sandreas.hansson@arm.com ''' 19010852Sandreas.hansson@arm.com 19110852Sandreas.hansson@arm.com assembler.symbols["maxOsz"] = ''' 19210852Sandreas.hansson@arm.com if (machInst.mode.submode == SixtyFourBitMode) 19310852Sandreas.hansson@arm.com env.dataSize = 8; 19410852Sandreas.hansson@arm.com else 19510852Sandreas.hansson@arm.com env.dataSize = 4; 19610852Sandreas.hansson@arm.com ''' 19710852Sandreas.hansson@arm.com 19810852Sandreas.hansson@arm.com def trimImm(width): 19910852Sandreas.hansson@arm.com return "adjustedImm = adjustedImm & mask(%s);" % width 20010852Sandreas.hansson@arm.com 20110852Sandreas.hansson@arm.com assembler.symbols["trimImm"] = trimImm 20210852Sandreas.hansson@arm.com 20310852Sandreas.hansson@arm.com def labeler(labelStr): 20410852Sandreas.hansson@arm.com return "label_%s" % labelStr 20510852Sandreas.hansson@arm.com 20610852Sandreas.hansson@arm.com assembler.symbols["label"] = labeler 20710852Sandreas.hansson@arm.com 20810852Sandreas.hansson@arm.com def rom_labeler(labelStr): 20910852Sandreas.hansson@arm.com return "romMicroPC(RomLabels::extern_label_%s)" % labelStr 21010852Sandreas.hansson@arm.com 21110852Sandreas.hansson@arm.com assembler.symbols["rom_label"] = rom_labeler 21210852Sandreas.hansson@arm.com 21310852Sandreas.hansson@arm.com def rom_local_labeler(labelStr): 21410852Sandreas.hansson@arm.com return "romMicroPC(RomLabels::label_%s)" % labelStr 21510852Sandreas.hansson@arm.com 21610852Sandreas.hansson@arm.com assembler.symbols["rom_local_label"] = rom_local_labeler 21710852Sandreas.hansson@arm.com 21810852Sandreas.hansson@arm.com def stack_index(index): 21910852Sandreas.hansson@arm.com return regIdx("NUM_FLOATREGS + (((%s) + 8) %% 8)" % index) 22010852Sandreas.hansson@arm.com 22110852Sandreas.hansson@arm.com assembler.symbols["st"] = stack_index 22210852Sandreas.hansson@arm.com 22310852Sandreas.hansson@arm.com macroopDict = assembler.assemble(microcode) 22410852Sandreas.hansson@arm.com 22510852Sandreas.hansson@arm.com decoder_output += mainRom.getDefinition() 22610852Sandreas.hansson@arm.com header_output += mainRom.getDeclaration() 22710852Sandreas.hansson@arm.com}}; 22810852Sandreas.hansson@arm.com