arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

X86: When decoding a memory only inst, fault on reg encodings, don't assert.

This change makes the decoder figure out if an instruction that only supports
memory is using a register encoding and decodes directly to "Unknown" which will
behave appropriately. This prevents other parts of the instruction creation
process from seeing the mismatch and asserting.

copyright: Change HP copyright on x86 code to be more friendly

X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.

X86: Use suffixes to differentiate XMM/MMX/GPR operands.

X86: Autogenerate macroop generateDisassemble function.

X86: Reorganize segmentation and implement segment selector movs.

X86: Implement the wrcr microop which writes a control register, and some control register work.

X86: Added some new versions of MOV and a new argument type tag.

X86: Implement microops and instructions that manipulate the flags register.

X86: Make fixed register operands ignore register index extensions from the REX prefix.
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.

X86: Allow RIP relative decode on -all- memory forms of operands.

Make the operand size reflect the size specifier on the operand tags, and implement NEG

Add a parameter type to read a register index from the opcode itself.

Implement rip relative addressing and put in some missing loads and stores.

Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.

Get rid of unnecessary output.

Implement a handful more instructions and differentiate macroops based on the operand types they expect.

Get rid of an unnecessary debug statement.

Fix the operand type tag parser to recognize multi character register names.

Minor comment fix up.

Make use of some of the REX prefix.

Use objects to pass around output code, and fix/implement a few things.

src/arch/x86/isa/formats/multi.isa:
Make the formats use objects to pass around output code.

Clean things up a little.

Big changes to use the new microcode assembler.

Reworked x86 a bit

Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa