Searched refs:tid (Results 1 - 25 of 108) sorted by relevance

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/gem5/tests/test-progs/pthread/src/
H A Dtest_pthread_create_para.cpp53 int tid; member in struct:__anon77
61 // write tid to this thread's output
62 (*my_args->output) = my_args->tid;
80 for ( int tid = 0; tid < MAX_N_WORKER_THREADS; ++tid ) {
83 t_args[tid].tid = tid;
84 t_args[tid]
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H A Dtest_pthread_create_seq.cpp52 int tid; member in struct:__anon78
60 // write tid to this thread's output
61 (*my_args->output) = my_args->tid;
79 for ( int tid = 0; tid < MAX_N_WORKER_THREADS; ++tid ) {
82 t_args[tid].tid = tid;
83 t_args[tid]
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H A Dtest_pthread_mutex.cpp101 for ( int tid = 0; tid < MAX_N_WORKER_THREADS; ++tid ) {
102 t_args[tid].nsteps = nsteps;
103 t_args[tid].shared_var = &shared_var;
104 t_args[tid].lock = &lock;
107 ret = pthread_create( threads + tid, nullptr, func, &t_args[tid] );
116 for ( int tid = 0; tid < n_worker_thread
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H A Dtest_atomic.cpp89 for ( size_t tid = 0; tid < MAX_N_WORKER_THREADS; tid++ ){
90 t_args[tid].nsteps = nsteps;
91 t_args[tid].shared_var = &shared_var;
94 ret = pthread_create( threads + tid, nullptr, func, &t_args[tid] );
104 for ( int tid = 0; tid < n_worker_threads; ++tid ) {
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/gem5/src/cpu/o3/
H A Drename_impl.hh79 for (uint32_t tid = 0; tid < Impl::MaxThreads; tid++) {
80 renameStatus[tid] = Idle;
81 renameMap[tid] = nullptr;
82 instsInProgress[tid] = 0;
83 loadsInProgress[tid] = 0;
84 storesInProgress[tid] = 0;
85 freeEntries[tid] = {0, 0, 0, 0};
86 emptyROB[tid]
259 clearStates(ThreadID tid) argument
375 squash(const InstSeqNum &squash_seq_num, ThreadID tid) argument
446 ThreadID tid = *threads++; local
467 ThreadID tid = *threads++; local
493 rename(bool &status_change, ThreadID tid) argument
549 renameInsts(ThreadID tid) argument
803 skidInsert(ThreadID tid) argument
860 ThreadID tid = *threads++; local
879 ThreadID tid = *threads++; local
910 block(ThreadID tid) argument
944 unblock(ThreadID tid) argument
965 doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) argument
1015 removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid) argument
1066 renameSrcRegs(const DynInstPtr &inst, ThreadID tid) argument
1133 renameDestRegs(const DynInstPtr &inst, ThreadID tid) argument
1187 calcFreeROBEntries(ThreadID tid) argument
1199 calcFreeIQEntries(ThreadID tid) argument
1211 calcFreeLQEntries(ThreadID tid) argument
1225 calcFreeSQEntries(ThreadID tid) argument
1251 readStallSignals(ThreadID tid) argument
1265 checkStall(ThreadID tid) argument
1297 readFreeEntries(ThreadID tid) argument
1333 checkSignalsAndUpdate(ThreadID tid) argument
1433 serializeAfter(InstQueue &inst_list, ThreadID tid) argument
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H A Drob_impl.hh69 for (ThreadID tid = 0; tid < numThreads; tid++) {
70 maxEntries[tid] = numEntries;
80 for (ThreadID tid = 0; tid < numThreads; tid++) {
81 maxEntries[tid] = part_amt;
90 for (ThreadID tid = 0; tid < numThread
162 ThreadID tid = *threads++; local
199 countInsts(ThreadID tid) argument
216 ThreadID tid = inst->threadNumber; local
243 retireHead(ThreadID tid) argument
278 isHeadReady(ThreadID tid) argument
297 ThreadID tid = *threads++; local
316 numFreeEntries(ThreadID tid) argument
323 doSquash(ThreadID tid) argument
410 ThreadID tid = *threads++; local
451 ThreadID tid = *threads++; local
480 squash(InstSeqNum squash_num, ThreadID tid) argument
510 readHeadInst(ThreadID tid) argument
525 readTailInst(ThreadID tid) argument
549 findInst(ThreadID tid, InstSeqNum squash_inst) argument
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H A Dcommit_impl.hh76 DefaultCommit<Impl>::processTrapEvent(ThreadID tid) argument
80 trapSquash[tid] = true;
110 for (ThreadID tid = 0; tid < numThreads; tid++) {
111 priority_list.push_back(tid);
115 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
116 commitStatus[tid]
376 clearStates(ThreadID tid) argument
459 deactivateThread(ThreadID tid) argument
479 ThreadID tid = *threads++; local
509 ThreadID tid = *threads++; local
521 numROBFreeEntries(ThreadID tid) argument
528 generateTrapEvent(ThreadID tid, Fault inst_fault) argument
546 generateTCEvent(ThreadID tid) argument
556 squashAll(ThreadID tid) argument
592 squashFromTrap(ThreadID tid) argument
610 squashFromTC(ThreadID tid) argument
627 squashFromSquashAfter(ThreadID tid) argument
645 squashAfter(ThreadID tid, const DynInstPtr &head_inst) argument
671 ThreadID tid = *threads++; local
698 ThreadID tid = *threads++; local
832 ThreadID tid = *threads++; local
944 ThreadID tid = *threads++; local
1010 ThreadID tid = head_inst->threadNumber; local
1158 ThreadID tid = head_inst->threadNumber; local
1349 ThreadID tid = inst->threadNumber; local
1397 ThreadID tid = inst->threadNumber; local
1480 ThreadID tid = activeThreads->front(); local
1500 ThreadID tid = *pri_iter; local
1531 ThreadID tid = *threads++; local
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H A Ddecode_impl.hh78 for (int tid = 0; tid < Impl::MaxThreads; tid++) {
79 stalls[tid] = {false};
80 decodeStatus[tid] = Idle;
81 bdelayDoneSeqNum[tid] = 0;
82 squashInst[tid] = nullptr;
83 squashAfterDelaySlot[tid] = 0;
96 DefaultDecode<Impl>::clearStates(ThreadID tid) argument
98 decodeStatus[tid]
257 block(ThreadID tid) argument
287 unblock(ThreadID tid) argument
306 squash(const DynInstPtr &inst, ThreadID tid) argument
358 squash(ThreadID tid) argument
406 skidInsert(ThreadID tid) argument
436 ThreadID tid = *threads++; local
454 ThreadID tid = *threads++; local
495 readStallSignals(ThreadID tid) argument
509 checkSignalsAndUpdate(ThreadID tid) argument
581 ThreadID tid = *threads++; local
602 decode(bool &status_change, ThreadID tid) argument
647 decodeInsts(ThreadID tid) argument
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H A Dfetch_impl.hh144 for (ThreadID tid = 0; tid < numThreads; tid++) {
145 decoder[tid] = new TheISA::Decoder(params->isa[tid]);
148 fetchBuffer[tid] = new uint8_t[fetchBufferSize];
334 DefaultFetch<Impl>::clearStates(ThreadID tid) argument
336 fetchStatus[tid] = Running;
337 pc[tid] = cpu->pcState(tid);
391 ThreadID tid = cpu->contextToThread(pkt->req->contextId()); local
501 drainStall(ThreadID tid) argument
547 deactivateThread(ThreadID tid) argument
573 ThreadID tid = inst->threadNumber; local
604 fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) argument
657 ThreadID tid = cpu->contextToThread(mem_req->contextId()); local
761 doSquash(const TheISA::PCState &newPC, const DynInstPtr squashInst, ThreadID tid) argument
813 squashFromDecode(const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid) argument
850 ThreadID tid = *threads++; local
883 squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid) argument
910 ThreadID tid = *threads++; local
967 ThreadID tid = *tid_itr; local
999 checkSignalsAndUpdate(ThreadID tid) argument
1104 buildInst(ThreadID tid, StaticInstPtr staticInst, StaticInstPtr curMacroop, TheISA::PCState thisPC, TheISA::PCState nextPC, bool trace) argument
1473 ThreadID tid = *thread; local
1529 ThreadID tid = *threads++; local
1566 ThreadID tid = *threads++; local
1599 pipelineIcacheAccesses(ThreadID tid) argument
1629 profileStall(ThreadID tid) argument
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H A Diew_impl.hh107 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
108 dispatchStatus[tid] = Running;
109 fetchRedirect[tid] = false;
308 for (ThreadID tid = 0; tid < numThreads; tid++) {
309 toRename->iewInfo[tid].usedIQ = true;
310 toRename->iewInfo[tid]
328 clearStates(ThreadID tid) argument
463 squash(ThreadID tid) argument
499 squashDueToBranch(const DynInstPtr& inst, ThreadID tid) argument
525 squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid) argument
552 block(ThreadID tid) argument
571 unblock(ThreadID tid) argument
666 skidInsert(ThreadID tid) argument
696 ThreadID tid = *threads++; local
713 ThreadID tid = *threads++; local
732 ThreadID tid = *threads++; local
765 checkStall(ThreadID tid) argument
782 checkSignalsAndUpdate(ThreadID tid) argument
860 emptyRenameInsts(ThreadID tid) argument
913 dispatch(ThreadID tid) argument
961 dispatchInsts(ThreadID tid) argument
1216 ThreadID tid = *threads++; local
1359 ThreadID tid = inst->threadNumber; local
1464 ThreadID tid = inst->threadNumber; local
1524 ThreadID tid = *threads++; local
1566 ThreadID tid = (*threads++); local
1636 ThreadID tid = inst->threadNumber; local
1668 ThreadID tid = inst->threadNumber; local
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H A Drob.hh123 const DynInstPtr &readHeadInst(ThreadID tid);
128 DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
140 DynInstPtr readTailInst(ThreadID tid);
148 void retireHead(ThreadID tid);
154 bool isHeadReady(ThreadID tid);
169 unsigned numFreeEntries(ThreadID tid);
172 unsigned getMaxEntries(ThreadID tid) argument
173 { return maxEntries[tid]; }
176 unsigned getThreadEntries(ThreadID tid) argument
177 { return threadEntries[tid]; }
184 isFull(ThreadID tid) argument
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H A Dcpu.cc222 for (ThreadID tid = 0; tid < numThreads; tid++) {
223 isa[tid] = params->isa[tid];
224 assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
233 commitRenameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
237 renameMap[tid].init(&regFile, TheISA::ZeroReg, fpZeroReg,
243 for (ThreadID tid = 0; tid < active_thread
633 activateThread(ThreadID tid) argument
651 deactivateThread(ThreadID tid) argument
698 activateContext(ThreadID tid) argument
737 suspendContext(ThreadID tid) argument
758 haltContext(ThreadID tid) argument
772 insertThread(ThreadID tid) argument
824 removeThread(ThreadID tid) argument
868 switchRenameMode(ThreadID tid, UnifiedFreeList* freelist) argument
912 trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst) argument
921 syscall(int64_t callnum, ThreadID tid, Fault *fault) argument
948 unserializeThread(CheckpointIn &cp, ThreadID tid) argument
1085 commitDrained(ThreadID tid) argument
1176 readMiscReg(int misc_reg, ThreadID tid) argument
1184 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
1191 setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument
1316 readArchIntReg(int reg_idx, ThreadID tid) argument
1327 readArchFloatReg(int reg_idx, ThreadID tid) argument
1388 readArchCCReg(int reg_idx, ThreadID tid) argument
1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument
1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument
1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument
1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument
1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument
1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument
1462 pcState(ThreadID tid) argument
1469 pcState(const TheISA::PCState &val, ThreadID tid) argument
1476 instAddr(ThreadID tid) argument
1483 nextInstAddr(ThreadID tid) argument
1490 microPC(ThreadID tid) argument
1497 squashFromTC(ThreadID tid) argument
1514 instDone(ThreadID tid, const DynInstPtr &inst) argument
1550 removeInstsNotInROB(ThreadID tid) argument
1595 removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) argument
1624 squashInstIt(const ListIt &instIt, ThreadID tid) argument
1721 wakeup(ThreadID tid) argument
1765 addThreadToExitingList(ThreadID tid) argument
1792 scheduleThreadExitEvent(ThreadID tid) argument
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H A Dcpu.hh231 void activateThread(ThreadID tid);
234 void deactivateThread(ThreadID tid);
237 void insertThread(ThreadID tid);
240 void removeThread(ThreadID tid);
249 void activateContext(ThreadID tid) override;
252 void suspendContext(ThreadID tid) override;
257 void haltContext(ThreadID tid) override;
265 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
266 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
268 /** Insert tid t
446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument
678 tcBase(ThreadID tid) argument
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/gem5/src/arch/null/
H A Dcpu_dummy.hh50 static void wakeup(ThreadID tid) { ; } argument
/gem5/src/cpu/pred/
H A Dindirect.hh52 ThreadID tid) = 0;
54 InstSeqNum seq_num, ThreadID tid) = 0;
55 virtual void commit(InstSeqNum seq_num, ThreadID tid,
57 virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
59 const TheISA::PCState& target, ThreadID tid) = 0;
60 virtual void genIndirectInfo(ThreadID tid, void* & indirect_history) = 0;
61 virtual void updateDirectionInfo(ThreadID tid, bool actually_taken) = 0;
62 virtual void deleteIndirectInfo(ThreadID tid, void * indirect_history) = 0;
63 virtual void changeDirectionPrediction(ThreadID tid,
H A Dbtb.cc75 DefaultBTB::getIndex(Addr instPC, ThreadID tid) argument
79 ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
91 DefaultBTB::valid(Addr instPC, ThreadID tid) argument
93 unsigned btb_idx = getIndex(instPC, tid);
101 && btb[btb_idx].tid == tid) {
112 DefaultBTB::lookup(Addr instPC, ThreadID tid)
114 unsigned btb_idx = getIndex(instPC, tid);
122 && btb[btb_idx].tid == tid) {
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H A Dbpred_unit.cc173 TheISA::PCState &pc, ThreadID tid)
190 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
192 tid,seqNum);
195 uncondBranch(tid, pc.instAddr(), bp_history);
198 pred_taken = lookup(tid, pc.instAddr(), bp_history);
200 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
202 tid, seqNum, pred_taken, pc);
207 iPred->genIndirectInfo(tid, indirect_history);
210 DPRINTF(Branch, "[tid:%i] [sn:%llu] "
212 "for PC %s\n", tid, seqNu
172 predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, TheISA::PCState &pc, ThreadID tid) argument
345 update(const InstSeqNum &done_sn, ThreadID tid) argument
368 squash(const InstSeqNum &squashed_sn, ThreadID tid) argument
413 squash(const InstSeqNum &squashed_sn, const TheISA::PCState &corrTarget, bool actually_taken, ThreadID tid) argument
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H A Dtage.hh78 virtual bool predict(ThreadID tid, Addr branch_pc, bool cond_branch,
86 void uncondBranch(ThreadID tid, Addr br_pc, void* &bp_history) override;
87 bool lookup(ThreadID tid, Addr branch_addr, void* &bp_history) override;
88 void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override;
89 void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
92 virtual void squash(ThreadID tid, void *bp_history) override;
H A Dbi_mode.hh60 void uncondBranch(ThreadID tid, Addr pc, void * &bp_history);
61 void squash(ThreadID tid, void *bp_history);
62 bool lookup(ThreadID tid, Addr branch_addr, void * &bp_history);
63 void btbUpdate(ThreadID tid, Addr branch_addr, void * &bp_history);
64 void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
68 void updateGlobalHistReg(ThreadID tid, bool taken);
H A Dtage.cc56 TAGE::update(ThreadID tid, Addr branch_pc, bool taken, void* bp_history, argument
69 tage->squash(tid, taken, tage_bi, corrTarget);
78 tage->condBranchUpdate(tid, branch_pc, taken, tage_bi, nrand,
83 tage->updateHistories(tid, branch_pc, taken, tage_bi, false, inst,
89 TAGE::squash(ThreadID tid, void *bp_history) argument
97 TAGE::predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) argument
101 return tage->tagePredict(tid, branch_pc, cond_branch, bi->tageBranchInfo);
105 TAGE::lookup(ThreadID tid, Addr branch_pc, void* &bp_history) argument
107 bool retval = predict(tid, branch_pc, true, bp_history);
113 tage->updateHistories(tid, branch_p
119 btbUpdate(ThreadID tid, Addr branch_pc, void* &bp_history) argument
126 uncondBranch(ThreadID tid, Addr br_pc, void* &bp_history) argument
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H A Dbtb.hh55 ThreadID tid; member in struct:DefaultBTB::BTBEntry
75 * @param tid The thread id.
78 TheISA::PCState lookup(Addr instPC, ThreadID tid);
82 * @param tid The thread id.
85 bool valid(Addr instPC, ThreadID tid);
90 * @param tid The thread id.
93 ThreadID tid);
100 inline unsigned getIndex(Addr instPC, ThreadID tid);
H A D2bit_local.hh69 virtual void uncondBranch(ThreadID tid, Addr pc, void * &bp_history);
78 bool lookup(ThreadID tid, Addr branch_addr, void * &bp_history);
87 void btbUpdate(ThreadID tid, Addr branch_addr, void * &bp_history);
94 void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
97 void squash(ThreadID tid, void *bp_history) argument
H A Dsimple_indirect.hh47 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
49 ThreadID tid);
50 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
51 void squash(InstSeqNum seq_num, ThreadID tid);
53 const TheISA::PCState& target, ThreadID tid);
54 void genIndirectInfo(ThreadID tid, void* & indirect_history);
55 void updateDirectionInfo(ThreadID tid, bool actually_taken);
56 void deleteIndirectInfo(ThreadID tid, void * indirect_history);
57 void changeDirectionPrediction(ThreadID tid, void * indirect_history,
80 Addr getSetIndex(Addr br_addr, unsigned ghr, ThreadID tid);
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/gem5/src/cpu/
H A Dsmt.hh57 * @param tid The thread to change.
61 void change_thread_state(ThreadID tid, int activate, int priority);
/gem5/src/cpu/minor/
H A Ddecode.cc73 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
76 name + ".inputBuffer" + std::to_string(tid), "insts",
82 Decode::getInput(ThreadID tid) argument
85 if (!inputBuffer[tid].empty()) {
86 const ForwardInstData &head = inputBuffer[tid].front();
88 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
95 Decode::popInput(ThreadID tid) argument
97 if (!inputBuffer[tid]
137 ThreadID tid = getScheduledThread(); local
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