cpu/o3/cpu.hh

231     void activateThread(ThreadID tid);
234     void deactivateThread(ThreadID tid);
237     void insertThread(ThreadID tid);
240     void removeThread(ThreadID tid);
249     void activateContext(ThreadID tid) override;
252     void suspendContext(ThreadID tid) override;
257     void haltContext(ThreadID tid) override;
265     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
266     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
268     /** Insert tid to the list of threads trying to exit */
269     void addThreadToExitingList(ThreadID tid);
272     bool isThreadExiting(ThreadID tid) const;
278     void scheduleThreadExitEvent(ThreadID tid);
287     void syscall(int64_t callnum, ThreadID tid, Fault *fault);
303     void commitDrained(ThreadID tid);
318     void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
323      * @param tid ThreadID
326     void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
340     RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
345     RegVal readMiscReg(int misc_reg, ThreadID tid);
348     void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
353     void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
424     RegVal readArchIntReg(int reg_idx, ThreadID tid);
426     RegVal readArchFloatReg(int reg_idx, ThreadID tid);
428     const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
430     VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
435     readArchVecLane(int reg_idx, int lId, ThreadID tid) const
437         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
446     setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
448         PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
454                                    const ElemIndex& ldx, ThreadID tid) const;
457                                                   ThreadID tid) const;
459     VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
461     RegVal readArchCCReg(int reg_idx, ThreadID tid);
468     void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
470     void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
473                            ThreadID tid);
475     void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
478                         const VecElem& val, ThreadID tid);
480     void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
483     void pcState(const TheISA::PCState &newPCState, ThreadID tid);
486     TheISA::PCState pcState(ThreadID tid);
489     Addr instAddr(ThreadID tid);
492     MicroPC microPC(ThreadID tid);
495     Addr nextInstAddr(ThreadID tid);
501     void squashFromTC(ThreadID tid);
509     void instDone(ThreadID tid, const DynInstPtr &inst);
518     void removeInstsNotInROB(ThreadID tid);
521     void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
524     inline void squashInstIt(const ListIt &instIt, ThreadID tid);
670     virtual void wakeup(ThreadID tid) override;
678     tcBase(ThreadID tid)
680         return thread[tid]->getTC();