Lines Matching refs:tid
107 for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
108 dispatchStatus[tid] = Running;
109 fetchRedirect[tid] = false;
308 for (ThreadID tid = 0; tid < numThreads; tid++) {
309 toRename->iewInfo[tid].usedIQ = true;
310 toRename->iewInfo[tid].freeIQEntries =
311 instQueue.numFreeEntries(tid);
313 toRename->iewInfo[tid].usedLSQ = true;
314 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
315 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
328 DefaultIEW<Impl>::clearStates(ThreadID tid)
330 toRename->iewInfo[tid].usedIQ = true;
331 toRename->iewInfo[tid].freeIQEntries =
332 instQueue.numFreeEntries(tid);
334 toRename->iewInfo[tid].usedLSQ = true;
335 toRename->iewInfo[tid].freeLQEntries = ldstQueue.numFreeLoadEntries(tid);
336 toRename->iewInfo[tid].freeSQEntries = ldstQueue.numFreeStoreEntries(tid);
400 for (ThreadID tid = 0; tid < numThreads; tid++) {
401 if (!insts[tid].empty()) {
402 DPRINTF(Drain, "%i: Insts not empty.\n", tid);
405 if (!skidBuffer[tid].empty()) {
406 DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid);
409 drained = drained && dispatchStatus[tid] == Running;
449 for (ThreadID tid = 0; tid < numThreads; tid++) {
450 dispatchStatus[tid] = Running;
451 fetchRedirect[tid] = false;
463 DefaultIEW<Impl>::squash(ThreadID tid)
465 DPRINTF(IEW, "[tid:%i] Squashing all instructions.\n", tid);
468 instQueue.squash(tid);
471 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
477 "[sn:%llu] [tid:%i]\n",
478 fromCommit->commitInfo[tid].doneSeqNum, tid);
480 while (!skidBuffer[tid].empty()) {
481 if (skidBuffer[tid].front()->isLoad()) {
482 toRename->iewInfo[tid].dispatchedToLQ++;
484 if (skidBuffer[tid].front()->isStore() ||
485 skidBuffer[tid].front()->isAtomic()) {
486 toRename->iewInfo[tid].dispatchedToSQ++;
489 toRename->iewInfo[tid].dispatched++;
491 skidBuffer[tid].pop();
494 emptyRenameInsts(tid);
499 DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
501 DPRINTF(IEW, "[tid:%i] [sn:%llu] Squashing from a specific instruction,"
503 "\n", tid, inst->seqNum, inst->pcState() );
505 if (!toCommit->squash[tid] ||
506 inst->seqNum < toCommit->squashedSeqNum[tid]) {
507 toCommit->squash[tid] = true;
508 toCommit->squashedSeqNum[tid] = inst->seqNum;
509 toCommit->branchTaken[tid] = inst->pcState().branching();
514 toCommit->pc[tid] = pc;
515 toCommit->mispredictInst[tid] = inst;
516 toCommit->includeSquashInst[tid] = false;
525 DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
527 DPRINTF(IEW, "[tid:%i] Memory violation, squashing violator and younger "
528 "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
535 if (!toCommit->squash[tid] ||
536 inst->seqNum <= toCommit->squashedSeqNum[tid]) {
537 toCommit->squash[tid] = true;
539 toCommit->squashedSeqNum[tid] = inst->seqNum;
540 toCommit->pc[tid] = inst->pcState();
541 toCommit->mispredictInst[tid] = NULL;
544 toCommit->includeSquashInst[tid] = true;
552 DefaultIEW<Impl>::block(ThreadID tid)
554 DPRINTF(IEW, "[tid:%i] Blocking.\n", tid);
556 if (dispatchStatus[tid] != Blocked &&
557 dispatchStatus[tid] != Unblocking) {
558 toRename->iewBlock[tid] = true;
564 skidInsert(tid);
566 dispatchStatus[tid] = Blocked;
571 DefaultIEW<Impl>::unblock(ThreadID tid)
573 DPRINTF(IEW, "[tid:%i] Reading instructions out of the skid "
574 "buffer %u.\n",tid, tid);
578 if (skidBuffer[tid].empty()) {
579 toRename->iewUnblock[tid] = true;
581 DPRINTF(IEW, "[tid:%i] Done unblocking.\n",tid);
582 dispatchStatus[tid] = Running;
666 DefaultIEW<Impl>::skidInsert(ThreadID tid)
670 while (!insts[tid].empty()) {
671 inst = insts[tid].front();
673 insts[tid].pop();
675 DPRINTF(IEW,"[tid:%i] Inserting [sn:%lli] PC:%s into "
676 "dispatch skidBuffer %i\n",tid, inst->seqNum,
677 inst->pcState(),tid);
679 skidBuffer[tid].push(inst);
682 assert(skidBuffer[tid].size() <= skidBufferMax &&
696 ThreadID tid = *threads++;
697 unsigned thread_count = skidBuffer[tid].size();
713 ThreadID tid = *threads++;
715 if (!skidBuffer[tid].empty())
732 ThreadID tid = *threads++;
734 if (dispatchStatus[tid] == Unblocking) {
765 DefaultIEW<Impl>::checkStall(ThreadID tid)
769 if (fromCommit->commitInfo[tid].robSquashing) {
770 DPRINTF(IEW,"[tid:%i] Stall from Commit stage detected.\n",tid);
772 } else if (instQueue.isFull(tid)) {
773 DPRINTF(IEW,"[tid:%i] Stall: IQ is full.\n",tid);
782 DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
791 if (fromCommit->commitInfo[tid].squash) {
792 squash(tid);
794 if (dispatchStatus[tid] == Blocked ||
795 dispatchStatus[tid] == Unblocking) {
796 toRename->iewUnblock[tid] = true;
800 dispatchStatus[tid] = Squashing;
801 fetchRedirect[tid] = false;
805 if (fromCommit->commitInfo[tid].robSquashing) {
806 DPRINTF(IEW, "[tid:%i] ROB is still squashing.\n", tid);
808 dispatchStatus[tid] = Squashing;
809 emptyRenameInsts(tid);
813 if (checkStall(tid)) {
814 block(tid);
815 dispatchStatus[tid] = Blocked;
819 if (dispatchStatus[tid] == Blocked) {
822 DPRINTF(IEW, "[tid:%i] Done blocking, switching to unblocking.\n",
823 tid);
825 dispatchStatus[tid] = Unblocking;
827 unblock(tid);
832 if (dispatchStatus[tid] == Squashing) {
835 DPRINTF(IEW, "[tid:%i] Done squashing, switching to running.\n",
836 tid);
838 dispatchStatus[tid] = Running;
850 for (ThreadID tid = 0; tid < numThreads; tid++)
851 assert(insts[tid].empty());
860 DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
862 DPRINTF(IEW, "[tid:%i] Removing incoming rename instructions\n", tid);
864 while (!insts[tid].empty()) {
866 if (insts[tid].front()->isLoad()) {
867 toRename->iewInfo[tid].dispatchedToLQ++;
869 if (insts[tid].front()->isStore() ||
870 insts[tid].front()->isAtomic()) {
871 toRename->iewInfo[tid].dispatchedToSQ++;
874 toRename->iewInfo[tid].dispatched++;
876 insts[tid].pop();
913 DefaultIEW<Impl>::dispatch(ThreadID tid)
922 if (dispatchStatus[tid] == Blocked) {
925 } else if (dispatchStatus[tid] == Squashing) {
931 if (dispatchStatus[tid] == Running ||
932 dispatchStatus[tid] == Idle) {
933 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
934 "dispatch.\n", tid);
936 dispatchInsts(tid);
937 } else if (dispatchStatus[tid] == Unblocking) {
945 dispatchInsts(tid);
952 skidInsert(tid);
955 unblock(tid);
961 DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
966 dispatchStatus[tid] == Unblocking ?
967 skidBuffer[tid] : insts[tid];
983 if (dispatchStatus[tid] == Unblocking) {
984 DPRINTF(IEW, "[tid:%i] Issue: Examining instruction from skid "
985 "buffer\n", tid);
991 DPRINTF(IEW, "[tid:%i] Issue: Adding PC %s [sn:%lli] [tid:%i] to "
993 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1001 DPRINTF(IEW, "[tid:%i] Issue: Squashed instruction encountered, "
1002 "not adding to IQ.\n", tid);
1010 toRename->iewInfo[tid].dispatchedToLQ++;
1013 toRename->iewInfo[tid].dispatchedToSQ++;
1016 toRename->iewInfo[tid].dispatched++;
1022 if (instQueue.isFull(tid)) {
1023 DPRINTF(IEW, "[tid:%i] Issue: IQ has become full.\n", tid);
1026 block(tid);
1031 toRename->iewUnblock[tid] = false;
1038 if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
1039 (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1040 (inst->isStore() && ldstQueue.sqFull(tid))) {
1041 DPRINTF(IEW, "[tid:%i] Issue: %s has become full.\n",tid,
1045 block(tid);
1050 toRename->iewUnblock[tid] = false;
1058 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1059 "encountered, adding to LSQ.\n", tid);
1074 toRename->iewInfo[tid].dispatchedToSQ++;
1076 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1077 "encountered, adding to LSQ.\n", tid);
1087 toRename->iewInfo[tid].dispatchedToLQ++;
1089 DPRINTF(IEW, "[tid:%i] Issue: Memory instruction "
1090 "encountered, adding to LSQ.\n", tid);
1110 toRename->iewInfo[tid].dispatchedToSQ++;
1117 DPRINTF(IEW, "[tid:%i] Issue: Nop instruction encountered, "
1118 "skipping.\n", tid);
1126 iewExecutedNop[tid]++;
1135 DPRINTF(IEW, "[tid:%i] Issue: Nonspeculative instruction "
1136 "encountered, skipping.\n", tid);
1157 toRename->iewInfo[tid].dispatched++;
1168 DPRINTF(IEW,"[tid:%i] Issue: Bandwidth Full. Blocking.\n", tid);
1169 block(tid);
1170 toRename->iewUnblock[tid] = false;
1173 if (dispatchStatus[tid] == Idle && dis_num_inst) {
1174 dispatchStatus[tid] = Running;
1216 ThreadID tid = *threads++;
1217 fetchRedirect[tid] = false;
1234 DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%llu].\n",
1243 DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1359 ThreadID tid = inst->threadNumber;
1361 if (!fetchRedirect[tid] ||
1362 !toCommit->squash[tid] ||
1363 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1370 fetchRedirect[tid] = true;
1372 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1374 tid,inst->seqNum);
1375 DPRINTF(IEW, "[tid:%i] [sn:%llu] "
1377 tid,inst->seqNum,inst->readPredTarg());
1378 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1380 tid,inst->seqNum,inst->pcState());
1382 squashDueToBranch(inst, tid);
1391 } else if (ldstQueue.violation(tid)) {
1397 violator = ldstQueue.getMemDepViolator(tid);
1404 fetchRedirect[tid] = true;
1410 squashDueToMemOrder(violator, tid);
1417 if (ldstQueue.violation(tid)) {
1420 DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1464 ThreadID tid = inst->threadNumber;
1469 iewInstsToCommit[tid]++;
1494 producerInst[tid]++;
1495 consumerInst[tid]+= dependents;
1497 writebackCount[tid]++;
1524 ThreadID tid = *threads++;
1526 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1528 checkSignalsAndUpdate(tid);
1529 dispatch(tid);
1566 ThreadID tid = (*threads++);
1568 DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1571 if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1572 !fromCommit->commitInfo[tid].squash &&
1573 !fromCommit->commitInfo[tid].robSquashing) {
1575 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1577 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1580 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1583 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1585 //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1586 if (fromCommit->commitInfo[tid].strictlyOrdered) {
1588 fromCommit->commitInfo[tid].strictlyOrderedLoad);
1589 fromCommit->commitInfo[tid].strictlyOrderedLoad->setAtCommit();
1592 fromCommit->commitInfo[tid].nonSpecSeqNum);
1597 toFetch->iewInfo[tid].iqCount =
1598 instQueue.getCount(tid);
1599 toFetch->iewInfo[tid].ldstqCount =
1600 ldstQueue.getCount(tid);
1602 toRename->iewInfo[tid].usedIQ = true;
1603 toRename->iewInfo[tid].freeIQEntries =
1604 instQueue.numFreeEntries(tid);
1605 toRename->iewInfo[tid].usedLSQ = true;
1607 toRename->iewInfo[tid].freeLQEntries =
1608 ldstQueue.numFreeLoadEntries(tid);
1609 toRename->iewInfo[tid].freeSQEntries =
1610 ldstQueue.numFreeStoreEntries(tid);
1615 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1616 tid, toRename->iewInfo[tid].dispatched);
1636 ThreadID tid = inst->threadNumber;
1650 iewExecutedBranches[tid]++;
1656 iewExecutedRefs[tid]++;
1659 iewExecLoadInsts[tid]++;
1668 ThreadID tid = inst->threadNumber;
1670 if (!fetchRedirect[tid] ||
1671 !toCommit->squash[tid] ||
1672 toCommit->squashedSeqNum[tid] > inst->seqNum) {
1675 fetchRedirect[tid] = true;
1677 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1679 tid,inst->seqNum);
1680 DPRINTF(IEW, "[tid:%i] [sn:%llu] Predicted target "
1682 tid,inst->seqNum,
1684 DPRINTF(IEW, "[tid:%i] [sn:%llu] Execute: "
1687 tid,inst->seqNum,
1691 squashDueToBranch(inst, tid);