Lines Matching refs:tid
222 for (ThreadID tid = 0; tid < numThreads; tid++) {
223 isa[tid] = params->isa[tid];
224 assert(RenameMode<TheISA::ISA>::equalsInit(isa[tid], isa[0]));
233 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
237 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
243 for (ThreadID tid = 0; tid < active_threads; tid++) {
248 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
249 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
254 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
255 commitRenameMap[tid].setEntry(
267 renameMap[tid].setEntry(rid, phys_reg);
268 commitRenameMap[tid].setEntry(rid, phys_reg);
277 renameMap[tid].setEntry(lrid, phys_elem);
278 commitRenameMap[tid].setEntry(lrid, phys_elem);
285 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
286 commitRenameMap[tid].setEntry(
292 renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
293 commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
311 for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
315 this->thread[tid] = new Thread(this, 0, NULL);
317 if (tid < params->workload.size()) {
319 tid, this->thread[tid]);
320 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
322 tid, params->workload[tid]);
324 //usedTids[tid] = true;
325 //threadMap[tid] = tid;
331 this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
333 tid, dummy_proc);
334 //usedTids[tid] = false;
354 o3_tc->thread = this->thread[tid];
357 this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
360 this->thread[tid]->tc = tc;
372 for (ThreadID tid = 0; tid < this->numThreads; tid++)
373 this->thread[tid]->setFuncExeInst(0);
594 for (ThreadID tid = 0; tid < numThreads; ++tid) {
597 thread[tid]->noSquashFromTC = true;
599 thread[tid]->initMemProxies(thread[tid]->getTC());
603 for (ThreadID tid = 0; tid < numThreads; tid++) {
604 ThreadContext *src_tc = threadContexts[tid];
610 for (int tid = 0; tid < numThreads; ++tid)
611 thread[tid]->noSquashFromTC = false;
621 for (int tid = 0; tid < numThreads; ++tid)
622 isa[tid]->startup(threadContexts[tid]);
633 FullO3CPU<Impl>::activateThread(ThreadID tid)
636 std::find(activeThreads.begin(), activeThreads.end(), tid);
638 DPRINTF(O3CPU, "[tid:%i] Calling activate thread.\n", tid);
642 DPRINTF(O3CPU, "[tid:%i] Adding to active threads list\n",
643 tid);
645 activeThreads.push_back(tid);
651 FullO3CPU<Impl>::deactivateThread(ThreadID tid)
655 std::find(activeThreads.begin(), activeThreads.end(), tid);
657 DPRINTF(O3CPU, "[tid:%i] Calling deactivate thread.\n", tid);
661 DPRINTF(O3CPU,"[tid:%i] Removing from active threads list\n",
662 tid);
666 fetch.deactivateThread(tid);
667 commit.deactivateThread(tid);
698 FullO3CPU<Impl>::activateContext(ThreadID tid)
703 activateThread(tid);
731 BaseCPU::activateContext(tid);
737 FullO3CPU<Impl>::suspendContext(ThreadID tid)
739 DPRINTF(O3CPU,"[tid:%i] Suspending Thread Context.\n", tid);
742 deactivateThread(tid);
753 BaseCPU::suspendContext(tid);
758 FullO3CPU<Impl>::haltContext(ThreadID tid)
761 DPRINTF(O3CPU,"[tid:%i] Halt Context called. Deallocating\n", tid);
764 deactivateThread(tid);
765 removeThread(tid);
772 FullO3CPU<Impl>::insertThread(ThreadID tid)
774 DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
779 src_tc = system->threadContexts[tid];
781 src_tc = tcBase(tid);
788 renameMap[tid].setEntry(reg_id, phys_reg);
796 renameMap[tid].setEntry(reg_id, phys_reg);
804 renameMap[tid].setEntry(reg_id, phys_reg);
809 //this->copyFromTC(tid);
812 pcState(src_tc->pcState(), tid);
816 activateContext(tid);
824 FullO3CPU<Impl>::removeThread(ThreadID tid)
826 DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
830 // this->copyToTC(tid);
839 commit.clearStates(tid);
840 fetch.clearStates(tid);
841 decode.clearStates(tid);
842 rename.clearStates(tid);
843 iew.clearStates(tid);
848 assert(iew.instQueue.getCount(tid) == 0);
849 assert(iew.ldstQueue.getCount(tid) == 0);
850 assert(commit.rob->isEmpty(tid));
868 FullO3CPU<Impl>::switchRenameMode(ThreadID tid, UnifiedFreeList* freelist)
870 auto pc = this->pcState(tid);
879 renameMap[tid].switchMode(vecMode);
880 commitRenameMap[tid].switchMode(vecMode);
881 renameMap[tid].switchFreeList(freelist);
912 FullO3CPU<Impl>::trap(const Fault &fault, ThreadID tid,
916 fault->invoke(this->threadContexts[tid], inst);
921 FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid, Fault *fault)
923 DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
929 ++(this->thread[tid]->funcExeInst);
932 this->thread[tid]->syscall(callnum, fault);
936 --(this->thread[tid]->funcExeInst);
941 FullO3CPU<Impl>::serializeThread(CheckpointOut &cp, ThreadID tid) const
943 thread[tid]->serialize(cp);
948 FullO3CPU<Impl>::unserializeThread(CheckpointIn &cp, ThreadID tid)
950 thread[tid]->unserialize(cp);
1085 FullO3CPU<Impl>::commitDrained(ThreadID tid)
1087 fetch.drainStall(tid);
1169 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
1171 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
1176 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
1179 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1186 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1194 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1316 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
1319 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1327 FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
1330 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1338 FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
1341 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1348 FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
1351 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1359 ThreadID tid) const -> const VecElem&
1361 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1368 FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
1371 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1378 FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
1381 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1388 FullO3CPU<Impl>::readArchCCReg(int reg_idx, ThreadID tid)
1391 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1399 FullO3CPU<Impl>::setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
1402 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1410 FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
1413 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1422 ThreadID tid)
1424 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1432 const VecElem& val, ThreadID tid)
1434 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1442 ThreadID tid)
1444 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1451 FullO3CPU<Impl>::setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
1454 PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
1462 FullO3CPU<Impl>::pcState(ThreadID tid)
1464 return commit.pcState(tid);
1469 FullO3CPU<Impl>::pcState(const TheISA::PCState &val, ThreadID tid)
1471 commit.pcState(val, tid);
1476 FullO3CPU<Impl>::instAddr(ThreadID tid)
1478 return commit.instAddr(tid);
1483 FullO3CPU<Impl>::nextInstAddr(ThreadID tid)
1485 return commit.nextInstAddr(tid);
1490 FullO3CPU<Impl>::microPC(ThreadID tid)
1492 return commit.microPC(tid);
1497 FullO3CPU<Impl>::squashFromTC(ThreadID tid)
1499 this->thread[tid]->noSquashFromTC = true;
1500 this->commit.generateTCEvent(tid);
1514 FullO3CPU<Impl>::instDone(ThreadID tid, const DynInstPtr &inst)
1518 thread[tid]->numInst++;
1519 thread[tid]->numInsts++;
1520 committedInsts[tid]++;
1524 comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
1527 thread[tid]->numOp++;
1528 thread[tid]->numOps++;
1529 committedOps[tid]++;
1538 DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %s "
1550 FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
1553 " list.\n", tid);
1561 } else if (rob.isEmpty(tid)) {
1566 end_it = (rob.readTailInst(tid))->getInstListIt();
1581 squashInstIt(inst_it, tid);
1589 squashInstIt(inst_it, tid);
1595 FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
1606 "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
1607 tid, seq_num, (*inst_iter)->seqNum);
1613 squashInstIt(inst_iter, tid);
1624 FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
1626 if ((*instIt)->threadNumber == tid) {
1628 "[tid:%i] [sn:%lli] PC %s\n",
1649 "[tid:%i] [sn:%lli] PC %s\n",
1680 cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
1721 FullO3CPU<Impl>::wakeup(ThreadID tid)
1723 if (this->thread[tid]->status() != ThreadContext::Suspended)
1729 this->threadContexts[tid]->activate();
1736 for (ThreadID tid = 0; tid < numThreads; tid++) {
1737 if (!tids[tid]) {
1738 tids[tid] = true;
1739 return tid;
1765 FullO3CPU<Impl>::addThreadToExitingList(ThreadID tid)
1767 DPRINTF(O3CPU, "Thread %d is inserted to exitingThreads list\n", tid);
1770 assert(tcBase(tid)->status() != ThreadContext::Halted);
1773 assert(exitingThreads.count(tid) == 0);
1780 exitingThreads.emplace(std::make_pair(tid, false));
1785 FullO3CPU<Impl>::isThreadExiting(ThreadID tid) const
1787 return exitingThreads.count(tid) == 1;
1792 FullO3CPU<Impl>::scheduleThreadExitEvent(ThreadID tid)
1794 assert(exitingThreads.count(tid) == 1);
1798 exitingThreads[tid] = true;