cpu/o3/commit_impl.hh

76 DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
80     trapSquash[tid] = true;
110         for (ThreadID tid = 0; tid < numThreads; tid++) {
111             priority_list.push_back(tid);
115     for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
116         commitStatus[tid] = Idle;
117         changedROBNumEntries[tid] = false;
118         trapSquash[tid] = false;
119         tcSquash[tid] = false;
120         squashAfterInst[tid] = nullptr;
121         pc[tid].set(0);
122         youngestSeqNum[tid] = 0;
123         lastCommitedSeqNum[tid] = 0;
124         trapInFlight[tid] = false;
125         committedStores[tid] = false;
126         checkEmptyROB[tid] = false;
127         renameMap[tid] = nullptr;
342     for (ThreadID tid = 0; tid < numThreads; tid++)
343         renameMap[tid] = &rm_ptr[tid];
361     for (ThreadID tid = 0; tid < numThreads; tid++) {
362         toIEW->commitInfo[tid].usedROB = true;
363         toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
364         toIEW->commitInfo[tid].emptyROB = true;
376 DefaultCommit<Impl>::clearStates(ThreadID tid)
378     commitStatus[tid] = Idle;
379     changedROBNumEntries[tid] = false;
380     checkEmptyROB[tid] = false;
381     trapInFlight[tid] = false;
382     committedStores[tid] = false;
383     trapSquash[tid] = false;
384     tcSquash[tid] = false;
385     pc[tid].set(0);
386     lastCommitedSeqNum[tid] = 0;
387     squashAfterInst[tid] = NULL;
426     for (ThreadID tid = 0; tid < numThreads; tid++) {
427         if (pc[tid].microPC() != 0)
447     for (ThreadID tid = 0; tid < numThreads; tid++) {
448         commitStatus[tid] = Idle;
449         changedROBNumEntries[tid] = false;
450         trapSquash[tid] = false;
451         tcSquash[tid] = false;
452         squashAfterInst[tid] = NULL;
459 DefaultCommit<Impl>::deactivateThread(ThreadID tid)
462             priority_list.end(), tid);
479         ThreadID tid = *threads++;
481         changedROBNumEntries[tid] = false;
484         if (commitStatus[tid] == TrapPending ||
485             commitStatus[tid] == FetchTrapPending) {
509         ThreadID tid = *threads++;
511         if (changedROBNumEntries[tid]) {
521 DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
523     return rob->numFreeEntries(tid);
528 DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
530     DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
533         [this, tid]{ processTrapEvent(tid); },
540     trapInFlight[tid] = true;
541     thread[tid]->trapPending = true;
546 DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
548     assert(!trapInFlight[tid]);
549     DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
551     tcSquash[tid] = true;
556 DefaultCommit<Impl>::squashAll(ThreadID tid)
562     InstSeqNum squashed_inst = rob->isEmpty(tid) ?
563         lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
568     youngestSeqNum[tid] = lastCommitedSeqNum[tid];
570     rob->squash(squashed_inst, tid);
571     changedROBNumEntries[tid] = true;
574     toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
578     toIEW->commitInfo[tid].squash = true;
582     toIEW->commitInfo[tid].robSquashing = true;
584     toIEW->commitInfo[tid].mispredictInst = NULL;
585     toIEW->commitInfo[tid].squashInst = NULL;
587     toIEW->commitInfo[tid].pc = pc[tid];
592 DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
594     squashAll(tid);
596     DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
598     thread[tid]->trapPending = false;
599     thread[tid]->noSquashFromTC = false;
600     trapInFlight[tid] = false;
602     trapSquash[tid] = false;
604     commitStatus[tid] = ROBSquashing;
610 DefaultCommit<Impl>::squashFromTC(ThreadID tid)
612     squashAll(tid);
614     DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
616     thread[tid]->noSquashFromTC = false;
617     assert(!thread[tid]->trapPending);
619     commitStatus[tid] = ROBSquashing;
622     tcSquash[tid] = false;
627 DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
630             "restarting at PC %s\n", pc[tid]);
632     squashAll(tid);
636     toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
637     squashAfterInst[tid] = NULL;
639     commitStatus[tid] = ROBSquashing;
645 DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst)
647     DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%llu]\n",
648             tid, head_inst->seqNum);
650     assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
651     commitStatus[tid] = SquashAfterPending;
652     squashAfterInst[tid] = head_inst;
671         ThreadID tid = *threads++;
675         committedStores[tid] = false;
677         if (commitStatus[tid] == ROBSquashing) {
679             if (rob->isDoneSquashing(tid)) {
680                 commitStatus[tid] = Running;
682                 DPRINTF(Commit,"[tid:%i] Still Squashing, cannot commit any"
683                         " insts this cycle.\n", tid);
684                 rob->doSquash(tid);
685                 toIEW->commitInfo[tid].robSquashing = true;
698         ThreadID tid = *threads++;
700         if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
705             const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
707             DPRINTF(Commit,"[tid:%i] Instruction [sn:%llu] PC %s is head of"
709                     tid, inst->seqNum, inst->pcState());
711         } else if (!rob->isEmpty(tid)) {
712             const DynInstPtr &inst = rob->readHeadInst(tid);
716             DPRINTF(Commit,"[tid:%i] Can't commit, Instruction [sn:%llu] PC "
718                     tid, inst->seqNum, inst->pcState());
721         DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
722                 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
832         ThreadID tid = *threads++;
836         if (trapSquash[tid]) {
837             assert(!tcSquash[tid]);
838             squashFromTrap(tid);
844             if (cpu->isThreadExiting(tid))
845                 cpu->scheduleThreadExitEvent(tid);
846         } else if (tcSquash[tid]) {
847             assert(commitStatus[tid] != TrapPending);
848             squashFromTC(tid);
849         } else if (commitStatus[tid] == SquashAfterPending) {
853             squashFromSquashAfter(tid);
859         if (fromIEW->squash[tid] &&
860             commitStatus[tid] != TrapPending &&
861             fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
863             if (fromIEW->mispredictInst[tid]) {
865                     "[tid:%i] Squashing due to branch mispred "
867                     tid,
868                     fromIEW->mispredictInst[tid]->instAddr(),
869                     fromIEW->squashedSeqNum[tid]);
872                     "[tid:%i] Squashing due to order violation [sn:%llu]\n",
873                     tid, fromIEW->squashedSeqNum[tid]);
876             DPRINTF(Commit, "[tid:%i] Redirecting to PC %#x\n",
877                     tid,
878                     fromIEW->pc[tid].nextInstAddr());
880             commitStatus[tid] = ROBSquashing;
884             InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
886             if (fromIEW->includeSquashInst[tid]) {
892             youngestSeqNum[tid] = squashed_inst;
894             rob->squash(squashed_inst, tid);
895             changedROBNumEntries[tid] = true;
897             toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
899             toIEW->commitInfo[tid].squash = true;
903             toIEW->commitInfo[tid].robSquashing = true;
905             toIEW->commitInfo[tid].mispredictInst =
906                 fromIEW->mispredictInst[tid];
907             toIEW->commitInfo[tid].branchTaken =
908                 fromIEW->branchTaken[tid];
909             toIEW->commitInfo[tid].squashInst =
910                                     rob->findInst(tid, squashed_inst);
911             if (toIEW->commitInfo[tid].mispredictInst) {
912                 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
913                      toIEW->commitInfo[tid].branchTaken = true;
918             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
921         if (commitStatus[tid] == ROBSquashing) {
944         ThreadID tid = *threads++;
946         if (changedROBNumEntries[tid]) {
947             toIEW->commitInfo[tid].usedROB = true;
948             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
951             changedROBNumEntries[tid] = false;
952             if (rob->isEmpty(tid))
953                 checkEmptyROB[tid] = true;
964         if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
965             !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
966             checkEmptyROB[tid] = false;
967             toIEW->commitInfo[tid].usedROB = true;
968             toIEW->commitInfo[tid].emptyROB = true;
969             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
1010         ThreadID tid = head_inst->threadNumber;
1012         assert(tid == commit_thread);
1015                 "Trying to commit head instruction, [tid:%i] [sn:%llu]\n",
1016                 tid, head_inst->seqNum);
1032             changedROBNumEntries[tid] = true;
1034             pc[tid] = head_inst->pcState();
1041             thread[tid]->funcExeInst++;
1048                 statCommittedInstType[tid][head_inst->opClass()]++;
1051                 changedROBNumEntries[tid] = true;
1054                 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1056                 if (tid == 0) {
1077                 cpu->traceFunctions(pc[tid].instAddr());
1079                 TheISA::advancePC(pc[tid], head_inst->staticInst);
1082                 lastCommitedSeqNum[tid] = head_inst->seqNum;
1087                     squashAfter(tid, head_inst);
1090                     if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1091                         !thread[tid]->trapPending) {
1095                         DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1096                         squashAfter(tid, head_inst);
1097                         cpu->commitDrained(tid);
1111                     assert(!thread[tid]->noSquashFromTC &&
1112                            !thread[tid]->trapPending);
1114                         oldpc = pc[tid].instAddr();
1115                         cpu->system->pcEventQueue.service(thread[tid]->getTC());
1117                     } while (oldpc != pc[tid].instAddr());
1134                     squashAfter(tid, head_inst);
1137                         "[tid:%i] [sn:%llu].\n",
1138                         head_inst->pcState(), tid ,head_inst->seqNum);
1158     ThreadID tid = head_inst->threadNumber;
1165         thread[tid]->funcExeInst--;
1176                 "instruction [tid:%i] [sn:%llu] "
1178                 tid, head_inst->seqNum, head_inst->pcState());
1180         if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1182                     "[tid:%i] [sn:%llu] "
1184                     tid, head_inst->seqNum);
1188         toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1195             DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1197                     tid, head_inst->seqNum, head_inst->pcState());
1198             toIEW->commitInfo[tid].strictlyOrdered = true;
1199             toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1221         DPRINTF(Commit, "Inst [tid:%i] [sn:%llu] PC %s has a fault\n",
1222                 tid, head_inst->seqNum, head_inst->pcState());
1224         if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1226                     "[tid:%i] [sn:%llu] "
1228                     tid, head_inst->seqNum);
1241         assert(!thread[tid]->noSquashFromTC);
1245         thread[tid]->noSquashFromTC = true;
1253         cpu->trap(inst_fault, tid,
1259         thread[tid]->noSquashFromTC = false;
1261         commitStatus[tid] = TrapPending;
1264             "[tid:%i] [sn:%llu] Committing instruction with fault\n",
1265             tid, head_inst->seqNum);
1269                 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1277         generateTrapEvent(tid, inst_fault);
1284         if (thread[tid]->profile) {
1285             thread[tid]->profilePC = head_inst->instAddr();
1286             ProfileNode *node = thread[tid]->profile->consume(
1287                     thread[tid]->getTC(), head_inst->staticInst);
1290                 thread[tid]->profileNode = node;
1294                 ThreadContext *tc = thread[tid]->getTC();
1300             "[tid:%i] [sn:%llu] Committing instruction with PC %s\n",
1301             tid, head_inst->seqNum, head_inst->pcState());
1304         head_inst->traceData->setCPSeq(thread[tid]->numOp);
1311                 "[tid:%i] [sn:%llu] Return Instruction Committed PC %s \n",
1312                 tid, head_inst->seqNum, head_inst->pcState());
1317         renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1322     rob->retireHead(tid);
1332         committedStores[tid] = true;
1349         ThreadID tid = inst->threadNumber;
1352             commitStatus[tid] != ROBSquashing &&
1353             commitStatus[tid] != TrapPending) {
1354             changedROBNumEntries[tid] = true;
1356             DPRINTF(Commit, "[tid:%i] [sn:%llu] Inserting PC %s into ROB.\n",
1357                     inst->seqNum, tid, inst->pcState());
1361             assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1363             youngestSeqNum[tid] = inst->seqNum;
1365             DPRINTF(Commit, "[tid:%i] [sn:%llu] "
1367                     inst->seqNum, tid, inst->pcState());
1381             DPRINTF(Commit, "[tid:%i] Marking PC %s, [sn:%llu] ready "
1397     ThreadID tid = inst->threadNumber;
1400         instsCommitted[tid]++;
1401     opsCommitted[tid]++;
1406         cpu->instDone(tid, inst);
1413         statComBranches[tid]++;
1419         statComRefs[tid]++;
1422             statComLoads[tid]++;
1426             statComAmos[tid]++;
1431         statComMembars[tid]++;
1436         statComInteger[tid]++;
1440         statComFloating[tid]++;
1443         statComVector[tid]++;
1447         statComFunctionCalls[tid]++;
1480         ThreadID tid = activeThreads->front();
1482         if (commitStatus[tid] == Running ||
1483             commitStatus[tid] == Idle ||
1484             commitStatus[tid] == FetchTrapPending) {
1485             return tid;
1500         ThreadID tid = *pri_iter;
1502         if (commitStatus[tid] == Running ||
1503             commitStatus[tid] == Idle ||
1504             commitStatus[tid] == FetchTrapPending) {
1506             if (rob->isHeadReady(tid)) {
1508                 priority_list.push_back(tid);
1510                 return tid;
1531         ThreadID tid = *threads++;
1533         if (!rob->isEmpty(tid) &&
1534             (commitStatus[tid] == Running ||
1535              commitStatus[tid] == Idle ||
1536              commitStatus[tid] == FetchTrapPending)) {
1538             if (rob->isHeadReady(tid)) {
1540                 const DynInstPtr &head_inst = rob->readHeadInst(tid);
1543                     oldest = tid;
1546                     oldest = tid;