Lines Matching refs:tid

78     for (int tid = 0; tid < Impl::MaxThreads; tid++) {
79 stalls[tid] = {false};
80 decodeStatus[tid] = Idle;
81 bdelayDoneSeqNum[tid] = 0;
82 squashInst[tid] = nullptr;
83 squashAfterDelaySlot[tid] = 0;
96 DefaultDecode<Impl>::clearStates(ThreadID tid)
98 decodeStatus[tid] = Idle;
99 stalls[tid].rename = false;
109 for (ThreadID tid = 0; tid < numThreads; ++tid) {
110 decodeStatus[tid] = Idle;
112 stalls[tid].rename = false;
216 for (ThreadID tid = 0; tid < numThreads; ++tid) {
217 assert(insts[tid].empty());
218 assert(skidBuffer[tid].empty());
226 for (ThreadID tid = 0; tid < numThreads; ++tid) {
227 if (!insts[tid].empty() || !skidBuffer[tid].empty() ||
228 (decodeStatus[tid] != Running && decodeStatus[tid] != Idle))
236 DefaultDecode<Impl>::checkStall(ThreadID tid) const
240 if (stalls[tid].rename) {
241 DPRINTF(Decode,"[tid:%i] Stall fom Rename stage detected.\n", tid);
257 DefaultDecode<Impl>::block(ThreadID tid)
259 DPRINTF(Decode, "[tid:%i] Blocking.\n", tid);
263 skidInsert(tid);
268 if (decodeStatus[tid] != Blocked) {
270 decodeStatus[tid] = Blocked;
272 if (toFetch->decodeUnblock[tid]) {
273 toFetch->decodeUnblock[tid] = false;
275 toFetch->decodeBlock[tid] = true;
287 DefaultDecode<Impl>::unblock(ThreadID tid)
290 if (skidBuffer[tid].empty()) {
291 DPRINTF(Decode, "[tid:%i] Done unblocking.\n", tid);
292 toFetch->decodeUnblock[tid] = true;
295 decodeStatus[tid] = Running;
299 DPRINTF(Decode, "[tid:%i] Currently unblocking.\n", tid);
306 DefaultDecode<Impl>::squash(const DynInstPtr &inst, ThreadID tid)
308 DPRINTF(Decode, "[tid:%i] [sn:%llu] Squashing due to incorrect branch "
309 "prediction detected at decode.\n", tid, inst->seqNum);
312 toFetch->decodeInfo[tid].branchMispredict = true;
313 toFetch->decodeInfo[tid].predIncorrect = true;
314 toFetch->decodeInfo[tid].mispredictInst = inst;
315 toFetch->decodeInfo[tid].squash = true;
316 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
317 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
318 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
319 toFetch->decodeInfo[tid].squashInst = inst;
320 if (toFetch->decodeInfo[tid].mispredictInst->isUncondCtrl()) {
321 toFetch->decodeInfo[tid].branchTaken = true;
327 if (decodeStatus[tid] == Blocked ||
328 decodeStatus[tid] == Unblocking) {
329 toFetch->decodeUnblock[tid] = 1;
333 decodeStatus[tid] = Squashing;
336 if (fromFetch->insts[i]->threadNumber == tid &&
344 while (!insts[tid].empty()) {
345 insts[tid].pop();
348 while (!skidBuffer[tid].empty()) {
349 skidBuffer[tid].pop();
353 cpu->removeInstsUntil(squash_seq_num, tid);
358 DefaultDecode<Impl>::squash(ThreadID tid)
360 DPRINTF(Decode, "[tid:%i] Squashing.\n",tid);
362 if (decodeStatus[tid] == Blocked ||
363 decodeStatus[tid] == Unblocking) {
365 toFetch->decodeUnblock[tid] = 1;
371 if (toFetch->decodeBlock[tid])
372 toFetch->decodeBlock[tid] = 0;
374 toFetch->decodeUnblock[tid] = 1;
379 decodeStatus[tid] = Squashing;
385 if (fromFetch->insts[i]->threadNumber == tid) {
393 while (!insts[tid].empty()) {
394 insts[tid].pop();
397 while (!skidBuffer[tid].empty()) {
398 skidBuffer[tid].pop();
406 DefaultDecode<Impl>::skidInsert(ThreadID tid)
410 while (!insts[tid].empty()) {
411 inst = insts[tid].front();
413 insts[tid].pop();
415 assert(tid == inst->threadNumber);
417 skidBuffer[tid].push(inst);
419 DPRINTF(Decode,"Inserting [tid:%d][sn:%lli] PC: %s into decode skidBuffer %i\n",
420 inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size());
425 assert(skidBuffer[tid].size() <= skidBufferMax);
436 ThreadID tid = *threads++;
437 if (!skidBuffer[tid].empty())
454 ThreadID tid = *threads++;
456 if (decodeStatus[tid] == Unblocking) {
495 DefaultDecode<Impl>::readStallSignals(ThreadID tid)
497 if (fromRename->renameBlock[tid]) {
498 stalls[tid].rename = true;
501 if (fromRename->renameUnblock[tid]) {
502 assert(stalls[tid].rename);
503 stalls[tid].rename = false;
509 DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
520 readStallSignals(tid);
523 if (fromCommit->commitInfo[tid].squash) {
525 DPRINTF(Decode, "[tid:%i] Squashing instructions due to squash "
526 "from commit.\n", tid);
528 squash(tid);
533 if (checkStall(tid)) {
534 return block(tid);
537 if (decodeStatus[tid] == Blocked) {
538 DPRINTF(Decode, "[tid:%i] Done blocking, switching to unblocking.\n",
539 tid);
541 decodeStatus[tid] = Unblocking;
543 unblock(tid);
548 if (decodeStatus[tid] == Squashing) {
551 DPRINTF(Decode, "[tid:%i] Done squashing, switching to running.\n",
552 tid);
554 decodeStatus[tid] = Running;
581 ThreadID tid = *threads++;
583 DPRINTF(Decode,"Processing [tid:%i]\n",tid);
584 status_change = checkSignalsAndUpdate(tid) || status_change;
586 decode(status_change, tid);
602 DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
611 if (decodeStatus[tid] == Blocked) {
613 } else if (decodeStatus[tid] == Squashing) {
619 if (decodeStatus[tid] == Running ||
620 decodeStatus[tid] == Idle) {
621 DPRINTF(Decode, "[tid:%i] Not blocked, so attempting to run "
622 "stage.\n",tid);
624 decodeInsts(tid);
625 } else if (decodeStatus[tid] == Unblocking) {
633 decodeInsts(tid);
638 skidInsert(tid);
641 status_change = unblock(tid) || status_change;
647 DefaultDecode<Impl>::decodeInsts(ThreadID tid)
651 int insts_available = decodeStatus[tid] == Unblocking ?
652 skidBuffer[tid].size() : insts[tid].size();
655 DPRINTF(Decode, "[tid:%i] Nothing to do, breaking out"
656 " early.\n",tid);
660 } else if (decodeStatus[tid] == Unblocking) {
661 DPRINTF(Decode, "[tid:%i] Unblocking, removing insts from skid "
662 "buffer.\n",tid);
664 } else if (decodeStatus[tid] == Running) {
669 &insts_to_decode = decodeStatus[tid] == Unblocking ?
670 skidBuffer[tid] : insts[tid];
672 DPRINTF(Decode, "[tid:%i] Sending instruction to rename.\n",tid);
681 DPRINTF(Decode, "[tid:%i] Processing instruction [sn:%lli] with "
682 "PC %s\n", tid, inst->seqNum, inst->pcState());
685 DPRINTF(Decode, "[tid:%i] Instruction %i with PC %s is "
687 tid, inst->seqNum, inst->pcState());
751 "[tid:%i] [sn:%llu] "
753 tid, inst->seqNum, target);
764 block(tid);