Searched refs:level (Results 1 - 25 of 47) sorted by relevance

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/gem5/src/dev/arm/
H A Dsmmu_v3_ptops.cc46 V7LPageTableOps::isValid(pte_t pte, unsigned level) const
48 switch (level) {
52 default: panic("bad level %d", level);
57 V7LPageTableOps::isLeaf(pte_t pte, unsigned level) const
59 switch (level) {
63 default: panic("bad level %d", level);
68 V7LPageTableOps::isWritable(pte_t pte, unsigned level, bool stage2) const argument
74 V7LPageTableOps::nextLevelPointer(pte_t pte, unsigned level) cons
161 isWritable(pte_t pte, unsigned level, bool stage2) const argument
259 isWritable(pte_t pte, unsigned level, bool stage2) const argument
358 isWritable(pte_t pte, unsigned level, bool stage2) const argument
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H A Dsmmu_v3_ptops.hh51 virtual bool isValid(pte_t pte, unsigned level) const = 0;
52 virtual bool isLeaf(pte_t pte, unsigned level) const = 0;
53 virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const = 0;
54 virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0;
55 virtual Addr index(Addr va, unsigned level) const = 0;
56 virtual Addr pageMask(pte_t pte, unsigned level) const = 0;
57 virtual Addr walkMask(unsigned level) const = 0;
64 bool isValid(pte_t pte, unsigned level) const override;
65 bool isLeaf(pte_t pte, unsigned level) const override;
66 bool isWritable(pte_t pte, unsigned level, boo
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H A Dsmmu_v3_transl.cc651 unsigned stage, unsigned level)
666 if ((1 << level) & walkCacheLevels) {
670 walkEntry = smmu.walkCache.lookup(addr, pt_ops->walkMask(level),
671 asid, vmid, stage, level);
676 indent, addr, asid, vmid, walkEntry->pa, stage, level);
680 indent, addr, asid, vmid, stage, level);
690 unsigned stage, unsigned level,
696 if (smmu.walkCacheEnable && ((1<<level) & walkCacheLevels)) {
704 e.level = level;
647 walkCacheLookup( Yield &yield, const WalkCache::Entry *&walkEntry, Addr addr, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level) argument
688 walkCacheUpdate(Yield &yield, Addr va, Addr vaMask, Addr pa, unsigned stage, unsigned level, bool leaf, uint8_t permissions) argument
729 walkStage1And2(Yield &yield, Addr addr, const PageTableOps *pt_ops, unsigned level, Addr walkPtr) argument
813 walkStage2(Yield &yield, Addr addr, bool final_tr, const PageTableOps *pt_ops, unsigned level, Addr walkPtr) argument
885 unsigned level; local
965 unsigned level = pt_ops->firstLevel(context.s2t0sz); local
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H A Dsmmu_v3_transl.hh123 unsigned stage, unsigned level);
126 unsigned stage, unsigned level,
131 unsigned level, Addr walkPtr);
135 unsigned level, Addr walkPtr);
174 unsigned stage, unsigned level);
H A Dsmmu_v3_caches.cc989 fatal("Number of WalkCache entries at each level must be "
1016 unsigned stage, unsigned level,
1021 Set &set = sets[pickSetIdx(va, vaMask, stage, level)];
1027 e.asid==asid && e.vmid==vmid && e.stage==stage && e.level==level)
1045 lookupsByStageLevel[stage-1][level]++;
1046 totalLookupsByStageLevel[stage-1][level]++;
1048 missesByStageLevel[stage-1][level]++;
1049 totalMissesByStageLevel[stage-1][level]++;
1063 assert(incoming.level<
1014 lookup(Addr va, Addr vaMask, uint16_t asid, uint16_t vmid, unsigned stage, unsigned level, bool updStats) argument
1192 pickEntryIdxToReplace(const Set &set, unsigned stage, unsigned level) argument
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/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_spawn_options.cpp44 sc_spawn_reset_base( bool async, bool level )
45 : m_async( async ), m_level(level)
52 bool m_level; // level indicating reset.
63 sc_spawn_reset( bool async, const SOURCE& source, bool level )
64 : sc_spawn_reset_base(async, level), m_source(source)
92 async_reset_signal_is ( const Port & port, bool level ) \
95 new sc_spawn_reset< Port >(true, port, level) ); \
100 reset_signal_is ( const Port & port, bool level ) \
103 new sc_spawn_reset< Port >(false, port, level) ); \
H A Dsc_spawn_options.h66 void async_reset_signal_is( const sc_in<bool>&, bool level );
67 void async_reset_signal_is( const sc_inout<bool>&, bool level );
68 void async_reset_signal_is( const sc_out<bool>&, bool level );
69 void async_reset_signal_is( const sc_signal_in_if<bool>&, bool level );
71 void reset_signal_is( const sc_in<bool>&, bool level );
72 void reset_signal_is( const sc_inout<bool>&, bool level );
73 void reset_signal_is( const sc_out<bool>&, bool level );
74 void reset_signal_is( const sc_signal_in_if<bool>&, bool level );
H A Dsc_reset.cpp78 sc_reset_finder( bool async, const sc_in<bool>* port_p, bool level,
80 sc_reset_finder( bool async, const sc_inout<bool>* port_p, bool level,
82 sc_reset_finder( bool async, const sc_out<bool>* port_p, bool level,
100 bool async, const sc_in<bool>* port_p, bool level, sc_process_b* target_p) :
101 m_async(async), m_level(level), m_next_p(0), m_in_p(port_p), m_inout_p(0),
109 bool async, const sc_inout<bool>* port_p, bool level, sc_process_b* target_p
111 m_async(async), m_level(level), m_next_p(0), m_in_p(0), m_inout_p(port_p),
119 bool async, const sc_out<bool>* port_p, bool level, sc_process_b* target_p
121 m_async(async), m_level(level), m_next_p(0), m_in_p(0), m_inout_p(0),
244 // level
99 sc_reset_finder( bool async, const sc_in<bool>* port_p, bool level, sc_process_b* target_p) argument
108 sc_reset_finder( bool async, const sc_inout<bool>* port_p, bool level, sc_process_b* target_p ) argument
118 sc_reset_finder( bool async, const sc_out<bool>* port_p, bool level, sc_process_b* target_p ) argument
246 reset_signal_is( bool async, const sc_in<bool>& port, bool level) argument
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H A Dsc_reset.h56 bool m_level; // level for reset.
92 bool level);
94 reset_signal_is( bool async, const sc_in<bool>& iface, bool level);
96 reset_signal_is( bool async, const sc_inout<bool>& iface, bool level);
98 reset_signal_is( bool async, const sc_out<bool>& iface, bool level);
H A Dsc_module.cpp289 sc_module::async_reset_signal_is( const sc_in<bool>& port, bool level )
291 sc_reset::reset_signal_is(true, port, level);
295 sc_module::async_reset_signal_is( const sc_inout<bool>& port, bool level )
297 sc_reset::reset_signal_is(true, port, level);
301 sc_module::async_reset_signal_is( const sc_out<bool>& port, bool level )
303 sc_reset::reset_signal_is(true, port, level);
307 sc_module::async_reset_signal_is(const sc_signal_in_if<bool>& iface, bool level) argument
309 sc_reset::reset_signal_is(true, iface, level);
341 sc_module::reset_signal_is( const sc_in<bool>& port, bool level )
343 sc_reset::reset_signal_is(false, port, level);
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H A Dsc_module.h166 void async_reset_signal_is( const sc_in<bool>& port, bool level );
167 void async_reset_signal_is( const sc_inout<bool>& port, bool level );
168 void async_reset_signal_is( const sc_out<bool>& port, bool level );
169 void async_reset_signal_is( const sc_signal_in_if<bool>& iface, bool level);
170 void reset_signal_is( const sc_in<bool>& port, bool level );
171 void reset_signal_is( const sc_inout<bool>& port, bool level );
172 void reset_signal_is( const sc_out<bool>& port, bool level );
173 void reset_signal_is( const sc_signal_in_if<bool>& iface, bool level );
/gem5/configs/common/
H A DGPUTLBConfig.py44 def TLB_constructor(level):
46 constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
47 assoc = options.L%(level)dTLBassoc, \
48 hitLatency = options.L%(level)dAccessLatency,\
49 missLatency2 = options.L%(level)dMissLatency,\
50 maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
51 accessDistance = options.L%(level)dAccessDistanceStat,\
58 def Coalescer_constructor(level):
61 options.L%(level)dProbesPerCycle, \
62 coalescingWindow = options.L%(level)dCoalescingWindo
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/gem5/src/mem/
H A Dstack_dist_calc.cc100 uint64_t sum_from_below, uint64_t level,
103 ++level;
123 panic_if(node_sum_l > (1 << (level - 1)),
124 "Error in sum left of level %ul, node index %ull, "
125 "Sum = %ull \n", level, node_n_index, node_sum_l);
127 panic_if(node_sum_r > (1 << (level - 1)),
128 "Error in sum right of level %ul, node index %ull, "
129 "Sum = %ull \n", level, node_n_index, node_sum_r);
164 tree[level].erase(node_n_index);
177 level, stack_dis
99 updateSum(Node* node, bool from_left, uint64_t sum_from_below, uint64_t level, uint64_t stack_dist, bool discard_node) argument
190 uint64_t level = 0; local
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H A Dstack_dist_calc.hh73 * from a lower level (e.g. membus to L2), can be marked (isMarked
77 * policy of the lower level affect the read/write accesses in an
194 * @param level level in the tree the calling node is located
200 uint64_t stack_dist, uint64_t level) const;
221 * @param level level in the tree the calling node is located
228 bool from_left, uint64_t sum_from_below, uint64_t level,
261 * @param level the level a
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/gem5/src/systemc/tests/systemc/1666-2011-compliance/mixed_child_procs/
H A Dmixed_child_procs.cpp125 void child_thread(int i, int level) argument
127 //cout << "child_thread " << i << " at level " << level << " called at " << sc_time_stamp() << endl;
128 if (level > 0 && !given_birth[i])
130 sc_spawn(sc_bind(&Top::child_thread, this, index++, level-1));
131 sc_spawn(sc_bind(&Top::child_method, this, index++, level-1), "h", &opt);
144 //cout << "child_thread " << i << " at level " << level << " awoke at " << sc_time_stamp() << endl;
153 //cout << "child_thread " << i << " at level " << level << " caugh
164 child_method(int i, int level) argument
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/gem5/src/arch/sparc/
H A Dinterrupts.hh93 int level = 15; local
94 while (level > 0 && !(1 << level & softint))
95 level--;
96 if (1 << level & softint)
97 return level;
236 int level = InterruptLevel(interrupts[IT_SOFT_INT]); local
237 return std::make_shared<InterruptLevelN>(level);
/gem5/src/systemc/tests/systemc/kernel/process_control/test07/
H A Dtest07.cpp45 , unsigned level = 0
48 if (!level)
55 std::cout << std::string( level + 1, ' ' )
65 dump_hierarchy( (*it)->get_child_objects(), level+1 );
68 if (!level)
/gem5/configs/example/
H A Dmemtest.py54 # memory, and then at each level a number of testers are attached,
77 # uppermost level of memory. The other integers (if any) specify the
78 # number of caches/testers connected at each level of the crossbar
88 help="Adds a non-coherent, last-level cache")
109 help = """Top-level clock for blocks running at system
120 # Determine the tester multiplier for each level as the
156 print("Error: Must have at least one level of caches")
164 print("Error: Must have testers at the uppermost level")
174 print("Error: Must have 1 or more caches at each level")
198 # Clone previous level an
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H A Dmemcheck.py72 # tree is a shared memory, and then at each level a number of
84 # caches/testers associated with the uppermost level of memory. The
86 # connected at each level of the crossbar hierarchy. The tester string
108 help = """Top-level clock for blocks running at system
135 print("Error: Must have at least one level of caches")
143 print("Error: Must have testers at the uppermost level")
153 print("Error: Must have 1 or more caches at each level")
156 # Determine the tester multiplier for each level as the string
161 print("Error: Must have at least one cache per level")
188 # Clone previous level an
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/gem5/ext/ply/example/yply/
H A Dylex.py61 t.lexer.level = 1
78 t.lexer.level += 1
82 t.lexer.level -= 1
83 if t.lexer.level == 0:
/gem5/ext/testlib/
H A Dlog.py189 def message(self, message, level=LogLevel.Info, bold=False, **metadata):
190 self.log_obj.log(LibraryMessage(message=message, level=level,
217 def test_message(self, test, message, level):
218 self.log_obj.log(TestMessage(message=message, level=level,
237 def test_message(self, message, level):
239 message=message, level=level)
/gem5/src/systemc/tests/systemc/1666-2011-compliance/child_proc_control/
H A Dchild_proc_control.cpp128 int level = 2; local
133 h = sc_spawn(sc_bind(&Top::child_proc, this, proc_count++, level));
140 void child_proc(int i, int level) argument
143 if (level > 0)
151 h = sc_spawn(sc_bind(&Top::child_proc, this, proc_count++, level-1));
/gem5/src/arch/x86/regs/
H A Dapic.hh97 Bitfield<14> level; member in namespace:X86ISA
/gem5/src/base/
H A Dtrie.hh86 dump(std::ostream &os, int level) argument
88 for (int i = 1; i < level; i++) {
91 if (level == 0)
98 kids[0]->dump(os, level + 1);
100 kids[1]->dump(os, level + 1);
/gem5/ext/ply/example/BASIC/
H A Dbasiclog.py12 level = logging.INFO, variable

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