1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_X86_APICREGS_HH__
32#define __ARCH_X86_APICREGS_HH__
33
34#include "base/bitunion.hh"
35
36namespace X86ISA
37{
38    enum ApicRegIndex
39    {
40        APIC_ID,
41        APIC_VERSION,
42        APIC_TASK_PRIORITY,
43        APIC_ARBITRATION_PRIORITY,
44        APIC_PROCESSOR_PRIORITY,
45        APIC_EOI,
46        APIC_LOGICAL_DESTINATION,
47        APIC_DESTINATION_FORMAT,
48        APIC_SPURIOUS_INTERRUPT_VECTOR,
49
50        APIC_IN_SERVICE_BASE,
51
52        APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16,
53
54        APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16,
55
56        APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16,
57        APIC_INTERRUPT_COMMAND_LOW,
58        APIC_INTERRUPT_COMMAND_HIGH,
59        APIC_LVT_TIMER,
60        APIC_LVT_THERMAL_SENSOR,
61        APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
62        APIC_LVT_LINT0,
63        APIC_LVT_LINT1,
64        APIC_LVT_ERROR,
65        APIC_INITIAL_COUNT,
66        APIC_CURRENT_COUNT,
67        APIC_DIVIDE_CONFIGURATION,
68
69        APIC_INTERNAL_STATE,
70
71        NUM_APIC_REGS
72    };
73
74    static inline ApicRegIndex
75    APIC_IN_SERVICE(int index)
76    {
77        return (ApicRegIndex)(APIC_IN_SERVICE_BASE + index);
78    }
79
80    static inline ApicRegIndex
81    APIC_TRIGGER_MODE(int index)
82    {
83        return (ApicRegIndex)(APIC_TRIGGER_MODE_BASE + index);
84    }
85
86    static inline ApicRegIndex
87    APIC_INTERRUPT_REQUEST(int index)
88    {
89        return (ApicRegIndex)(APIC_INTERRUPT_REQUEST_BASE + index);
90    }
91
92    BitUnion32(InterruptCommandRegLow)
93        Bitfield<7, 0> vector;
94        Bitfield<10, 8> deliveryMode;
95        Bitfield<11> destMode;
96        Bitfield<12> deliveryStatus;
97        Bitfield<14> level;
98        Bitfield<15> trigger;
99        Bitfield<19, 18> destShorthand;
100    EndBitUnion(InterruptCommandRegLow)
101
102    BitUnion32(InterruptCommandRegHigh)
103        Bitfield<31, 24> destination;
104    EndBitUnion(InterruptCommandRegHigh)
105}
106
107#endif
108