configs/example/memtest.py

54 # memory, and then at each level a number of testers are attached,
77 # uppermost level of memory. The other integers (if any) specify the
78 # number of caches/testers connected at each level of the crossbar
88                   help="Adds a non-coherent, last-level cache")
109                   help = """Top-level clock for blocks running at system
120      # Determine the tester multiplier for each level as the
156           print("Error: Must have at least one level of caches")
164           print("Error: Must have testers at the uppermost level")
174                print("Error: Must have 1 or more caches at each level")
198      # Clone previous level and update params
208      # Swap the inclusivity/exclusivity at each level. L2 is mostly
234 # For each level, track the next subsys index to use
239 def make_cache_level(ncaches, prototypes, level, next_cache):
242      index = next_subsys_index[level]
243      next_subsys_index[level] += 1
248      setattr(system, 'l%dsubsys%d' % (level, index), subsys)
251      ntesters = testerspec[len(cachespec) - level]
254      # (smaller level) get a smaller portion of the overall bandwidth,
256      # testers closer to the memory (larger level) to prevent them
258      limit = (len(cachespec) - level + 1) * 100000000
259      testers = [proto_tester(interval = 10 * (level * level + 1),
265      if level != 0:
267           # we do this even with a single element on this level
275           # on this level
282                make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
288                print("Error: No next-level cache at top level")
302 # Top level call to create the cache hierarchy, bottom up
305 # Connect the lowest level crossbar to the last-level cache and memory