dev/arm/smmu_v3_transl.cc

651         unsigned stage, unsigned level)
666     if ((1 << level) & walkCacheLevels) {
670         walkEntry = smmu.walkCache.lookup(addr, pt_ops->walkMask(level),
671                                           asid, vmid, stage, level);
676                     indent, addr, asid, vmid, walkEntry->pa, stage, level);
680                     indent, addr, asid, vmid, stage, level);
690                                         unsigned stage, unsigned level,
696     if (smmu.walkCacheEnable && ((1<<level) & walkCacheLevels)) {
704         e.level = level;
715                 e.pa, e.leaf, e.stage, e.level);
731                                        unsigned level, Addr walkPtr)
739     for (; level <= pt_ops->lastLevel(); level++) {
740         Addr pte_addr = walkPtr + pt_ops->index(addr, level);
743                 level, pte_addr);
745         doReadPTE(yield, addr, pte_addr, &pte, 1, level);
748                 level, pte, pte_addr);
754         bool valid = pt_ops->isValid(pte, level);
755         bool leaf  = pt_ops->isLeaf(pte, level);
766             !pt_ops->isWritable(pte, level, false))
775         walkPtr = pt_ops->nextLevelPointer(pte, level);
788         walkCacheUpdate(yield, addr, pt_ops->walkMask(level), walkPtr,
789                         1, level, leaf, 0);
794     tr.addrMask = pt_ops->pageMask(pte, level);
796     tr.writable = pt_ops->isWritable(pte, level, false);
807                     1, level, true, tr.writable);
815                                    unsigned level, Addr walkPtr)
823     for (; level <= pt_ops->lastLevel(); level++) {
824         Addr pte_addr = walkPtr + pt_ops->index(addr, level);
827                 level, pte_addr);
829         doReadPTE(yield, addr, pte_addr, &pte, 2, level);
832                 level, pte, pte_addr);
838         bool valid = pt_ops->isValid(pte, level);
839         bool leaf  = pt_ops->isLeaf(pte, level);
850             !pt_ops->isWritable(pte, level, true))
859         walkPtr = pt_ops->nextLevelPointer(pte, level);
862             walkCacheUpdate(yield, addr, pt_ops->walkMask(level), walkPtr,
863                             2, level, leaf,
864                             leaf ? pt_ops->isWritable(pte, level, true) : 0);
871     tr.addrMask = pt_ops->pageMask(pte, level);
873     tr.writable = pt_ops->isWritable(pte, level, true);
885     unsigned level;
887     // Level here is actually (level+1) so we can count down
889     for (level = pt_ops->lastLevel() + 1;
890         level > pt_ops->firstLevel(context.t0sz);
891         level--)
894                         context.asid, context.vmid, 1, level-1);
900     // Correct level (see above).
901     level -= 1;
911             tr = walkStage1And2(yield, addr, pt_ops, level+1, walk_ep->pa);
965     unsigned level = pt_ops->firstLevel(context.s2t0sz);
968         // Level here is actually (level+1) so we can count down
970         for (level = pt_ops->lastLevel() + 1;
971             level > pt_ops->firstLevel(context.s2t0sz);
972             level--)
975                             0, context.vmid, 2, level-1);
981         // Correct level (see above).
982         level -= 1;
994                             level + 1, walk_ep->pa);
1358             panic("Invalid level 1 stream table descriptor");
1362             panic("StreamID %d out of level 1 descriptor range %d",
1469                                   unsigned level)