Searched refs:imm (Results 1 - 25 of 48) sorted by relevance

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/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.h42 lui(const uint32_t imm) argument
45 asm volatile("lui %0,%1" : "=r" (rd) : "i" (imm));
50 auipc(const uint64_t imm) argument
53 asm volatile("auipc %0,%1" : "=r" (rd) : "i" (imm));
56 return rd >= imm;
217 addi(int64_t rs1, const int16_t imm) argument
220 IOP("addi", rd, rs1, imm);
225 slti(int64_t rs1, const int16_t imm) argument
228 IOP("slti", rd, rs1, imm);
233 sltiu(uint64_t rs1, const uint16_t imm) argument
241 xori(uint64_t rs1, const uint16_t imm) argument
249 ori(uint64_t rs1, const uint16_t imm) argument
257 andi(uint64_t rs1, const uint16_t imm) argument
265 slli(int64_t rs1, const uint16_t imm) argument
273 srli(uint64_t rs1, const uint16_t imm) argument
281 srai(int64_t rs1, const uint16_t imm) argument
369 addiw(int64_t rs1, const int16_t imm) argument
377 slliw(int64_t rs1, const uint16_t imm) argument
385 srliw(uint64_t rs1, const uint16_t imm) argument
393 sraiw(int64_t rs1, const uint16_t imm) argument
[all...]
H A Drv64c.h38 #define CIOP(op, r, imm) asm volatile(op " %0,%1" : "+r" (r) : "i" (imm));
45 c_li(const int8_t imm) argument
48 CIOP("c.li", rd, imm);
53 c_lui(const int8_t imm) argument
56 CIOP("c.lui", rd, imm);
61 c_addi(int64_t r, const int8_t imm) argument
63 CIOP("c.addi", r, imm);
68 c_addiw(int64_t r, const int8_t imm) argument
70 CIOP("c.addiw", r, imm);
75 c_addi4spn(const int16_t imm) argument
104 c_andi(uint64_t r, uint8_t imm) argument
[all...]
H A Dinsttest.h39 #define IOP(inst, rd, rs1, imm) \
40 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "i" (imm))
/gem5/src/arch/sparc/insts/
H A Dmem.hh67 Mem(mnem, _machInst, __opClass), imm(sext<13>(bits(_machInst, 12, 0)))
73 const int32_t imm; member in class:SparcISA::MemImm
H A Dinteger.cc63 if (imm == 0) {
67 ccprintf(os, " %#x, ", imm);
71 } else if (imm == 0) {
108 ccprintf(response, "%#x", imm);
121 ccprintf(response, "%%hi(%#x), ", imm);
H A Dblockmem.hh81 imm(sext<13>(bits(_machInst, 12, 0)))
87 const int32_t imm; member in class:SparcISA::BlockMemImmMicro
H A Dblockmem.cc76 if (imm >= 0)
77 ccprintf(response, " + 0x%x ]", imm);
79 ccprintf(response, " + -0x%x ]", -imm);
H A Dmem.cc82 if (imm >= 0)
83 ccprintf(response, "%#x]", imm);
85 ccprintf(response, "-%#x]", -imm);
H A Dbranch.hh112 imm(sext<13>(bits(_machInst, 12, 0)))
118 int32_t imm; member in class:SparcISA::BranchImm13
H A Dinteger.hh70 IntOp(mnem, _machInst, __opClass), imm(_imm)
73 int64_t imm; member in class:SparcISA::IntOpImm
H A Dpriv.hh92 Priv(mnem, _machInst, __opClass), imm(bits(_machInst, 12, 0))
95 int32_t imm; member in class:SparcISA::PrivImm
/gem5/src/arch/arm/insts/
H A Dsve_mem.cc54 if (imm != 0) {
55 ccprintf(ss, ", #%d, mul vl", imm);
70 if (imm != 0) {
71 ccprintf(ss, ", #%d, mul vl", imm);
109 if (imm != 0) {
110 ccprintf(ss, ", #%d, mul vl", imm);
H A Dpred_inst.cc52 uint32_t imm = machInst.imm; local
53 imm = (imm << (32 - rotate)) | (imm >> rotate);
60 imm);
74 imm);
83 INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
H A Dmem64.cc95 if (imm)
96 ccprintf(ss, ", #%d", imm);
111 if (imm)
112 ccprintf(ss, ", #%d", imm);
129 if (imm)
130 ccprintf(ss, ", #%d", imm);
140 ccprintf(ss, ", #%d]!", imm);
149 if (imm)
150 ccprintf(ss, "], #%d", imm);
194 ccprintf(ss, ", #%d", pc + imm);
[all...]
H A Dsve_mem.hh54 uint64_t imm; member in class:ArmISA::SveMemVecFillSpill
65 dest(_dest), base(_base), imm(_imm),
79 uint64_t imm; member in class:ArmISA::SveMemPredFillSpill
90 dest(_dest), base(_base), imm(_imm),
131 uint64_t imm; member in class:ArmISA::SveContigMemSI
142 dest(_dest), gp(_gp), base(_base), imm(_imm),
H A Dmisc.hh75 uint32_t imm; member in class:MsrImmOp
79 MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
106 uint32_t imm; member in class:MrrcOp
112 dest2(_dest2), imm(_imm)
125 uint32_t imm; member in class:McrrOp
131 dest(_dest), imm(_imm)
141 uint64_t imm; member in class:ImmOp
145 PredOp(mnem, _machInst, __opClass), imm(_imm)
156 uint64_t imm; member in class:RegImmOp
160 PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_im
186 uint64_t imm; member in class:RegImmRegOp
205 uint64_t imm; member in class:RegRegRegImmOp
259 uint64_t imm; member in class:RegRegImmOp
277 uint64_t imm; member in class:MiscRegRegImmOp
295 uint64_t imm; member in class:RegMiscRegImmOp
348 uint64_t imm; member in class:RegImmRegShiftOp
[all...]
H A Dbranch.hh53 int32_t imm; member in class:ArmISA::BranchImm
58 PredOp(mnem, _machInst, __opClass), imm(_imm)
127 int32_t imm; member in class:ArmISA::BranchImmReg
133 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
H A Dmisc64.hh49 uint64_t imm; member in class:ImmOp64
53 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
85 uint64_t imm; member in class:RegRegRegImmOp64
91 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
150 uint32_t imm; member in class:MiscRegImmOp64
156 dest(_dest), imm(_imm)
175 uint32_t imm; member in class:MiscRegRegImmOp64
181 dest(_dest), op1(_op1), imm(_imm)
193 uint32_t imm; member in class:RegMiscRegImmOp64
199 dest(_dest), op1(_op1), imm(_im
211 const uint32_t imm; member in class:MiscRegImplDefined64
[all...]
H A Dbranch64.cc49 pcs.instNPC(pcs.pc() + imm);
58 pcs.instNPC(pcs.pc() + imm);
78 printTarget(ss, pc + imm, symtab);
88 printTarget(ss, pc + imm, symtab);
130 printTarget(ss, pc + imm, symtab);
H A Dsve.cc200 ss << imm; local
215 ss << imm; local
229 ss << imm; local
244 ss << imm; local
258 ss << imm; local
385 ss << imm; local
416 ss << imm; local
457 if (imm != 0x1f) {
459 ss << sveDisasmPredCountImm(imm);
496 ss << imm; local
714 ss << imm; local
728 ss << imm; local
812 ss << imm; local
820 sveDisasmPredCountImm(uint8_t imm) argument
852 sveDecodePredCount(uint8_t imm, unsigned int num_elems) argument
895 sveExpandFpImmAddSub(uint8_t imm, uint8_t size) argument
917 sveExpandFpImmMaxMin(uint8_t imm, uint8_t size) argument
936 sveExpandFpImmMul(uint8_t imm, uint8_t size) argument
[all...]
H A Dbranch64.hh50 int64_t imm; member in class:ArmISA::BranchImm64
55 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
129 int64_t imm; member in class:ArmISA::BranchImmReg64
135 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
H A Dsve.hh212 uint64_t imm; member in class:ArmISA::SveUnaryWideImmUnpredOp
218 dest(_dest), imm(_imm)
228 uint64_t imm; member in class:ArmISA::SveUnaryWideImmPredOp
237 dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging)
247 uint64_t imm; member in class:ArmISA::SveBinImmUnpredConstrOp
253 dest(_dest), op1(_op1), imm(_imm)
263 uint64_t imm; member in class:ArmISA::SveBinImmPredOp
268 dest(_dest), gp(_gp), imm(_imm)
278 uint64_t imm; member in class:ArmISA::SveBinWideImmUnpredOp
284 dest(_dest), imm(_im
402 uint64_t imm; member in class:ArmISA::SveCmpImmOp
433 uint64_t imm; member in class:ArmISA::SveTerImmUnpredOp
477 uint8_t imm; member in class:ArmISA::SvePtrueOp
510 int64_t imm; member in class:ArmISA::SveIntCmpImmOp
552 uint8_t imm; member in class:ArmISA::SveElemCountOp
739 uint64_t imm; member in class:ArmISA::SveBinImmUnpredDestrOp
754 uint64_t imm; member in class:ArmISA::SveBinImmIdxUnpredOp
786 uint64_t imm; member in class:ArmISA::SveDotProdIdxOp
838 uint8_t rot, imm; member in class:ArmISA::SveComplexIdxOp
[all...]
H A Ddata64.hh52 uint64_t imm; member in class:ArmISA::DataXImmOp
57 dest(_dest), op1(_op1), imm(_imm)
68 uint64_t imm; member in class:ArmISA::DataXImmOnlyOp
73 dest(_dest), imm(_imm)
136 uint64_t imm; member in class:ArmISA::DataX1RegImmOp
141 imm(_imm)
184 uint64_t imm; member in class:ArmISA::DataX2RegImmOp
190 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
217 uint64_t imm; member in class:ArmISA::DataXCondCompImmOp
225 op1(_op1), imm(_im
[all...]
/gem5/ext/systemc/src/sysc/qt/time/
H A Dprim36 imm = times[m "_" test_callimm];
39 printf ("%s|%1.3f|%1.3f|%1.3f|%1.3f\n", m, ind, imm, add, load);
/gem5/src/arch/riscv/insts/
H A Dstandard.hh64 I imm; member in class:RiscvISA::ImmOp
67 : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)

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