1/* 2 * Copyright (c) 2006-2007 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 * Gabe Black 30 * Steve Reinhardt 31 */ 32 33#include "arch/sparc/insts/integer.hh" 34 35namespace SparcISA 36{ 37 38//////////////////////////////////////////////////////////////////// 39// 40// Integer operate instructions 41// 42 43bool 44IntOp::printPseudoOps(std::ostream &os, Addr pc, 45 const SymbolTable *symbab) const 46{ 47 if (!std::strcmp(mnemonic, "or") && _srcRegIdx[0].index() == 0) { 48 printMnemonic(os, "mov"); 49 printSrcReg(os, 1); 50 ccprintf(os, ", "); 51 printDestReg(os, 0); 52 return true; 53 } 54 return false; 55} 56 57bool 58IntOpImm::printPseudoOps(std::ostream &os, Addr pc, 59 const SymbolTable *symbab) const 60{ 61 if (!std::strcmp(mnemonic, "or")) { 62 if (_numSrcRegs > 0 && _srcRegIdx[0].index() == 0) { 63 if (imm == 0) { 64 printMnemonic(os, "clr"); 65 } else { 66 printMnemonic(os, "mov"); 67 ccprintf(os, " %#x, ", imm); 68 } 69 printDestReg(os, 0); 70 return true; 71 } else if (imm == 0) { 72 printMnemonic(os, "mov"); 73 printSrcReg(os, 0); 74 ccprintf(os, ", "); 75 printDestReg(os, 0); 76 return true; 77 } 78 } 79 return false; 80} 81 82std::string 83IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 84{ 85 std::stringstream response; 86 87 if (printPseudoOps(response, pc, symtab)) 88 return response.str(); 89 printMnemonic(response, mnemonic); 90 printRegArray(response, _srcRegIdx, _numSrcRegs); 91 if (_numDestRegs && _numSrcRegs) 92 response << ", "; 93 printDestReg(response, 0); 94 return response.str(); 95} 96 97std::string 98IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const 99{ 100 std::stringstream response; 101 102 if (printPseudoOps(response, pc, symtab)) 103 return response.str(); 104 printMnemonic(response, mnemonic); 105 printRegArray(response, _srcRegIdx, _numSrcRegs); 106 if (_numSrcRegs > 0) 107 response << ", "; 108 ccprintf(response, "%#x", imm); 109 if (_numDestRegs > 0) 110 response << ", "; 111 printDestReg(response, 0); 112 return response.str(); 113} 114 115std::string 116SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const 117{ 118 std::stringstream response; 119 120 printMnemonic(response, mnemonic); 121 ccprintf(response, "%%hi(%#x), ", imm); 122 printDestReg(response, 0); 123 return response.str(); 124} 125 126} 127