113955Sgiacomo.gabrielli@arm.com/* 213955Sgiacomo.gabrielli@arm.com * Copyright (c) 2017 ARM Limited 313955Sgiacomo.gabrielli@arm.com * All rights reserved 413955Sgiacomo.gabrielli@arm.com * 513955Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613955Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713955Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813955Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913955Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013955Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113955Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213955Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313955Sgiacomo.gabrielli@arm.com * 1413955Sgiacomo.gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 1513955Sgiacomo.gabrielli@arm.com * modification, are permitted provided that the following conditions are 1613955Sgiacomo.gabrielli@arm.com * met: redistributions of source code must retain the above copyright 1713955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 1813955Sgiacomo.gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 1913955Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 2013955Sgiacomo.gabrielli@arm.com * documentation and/or other materials provided with the distribution; 2113955Sgiacomo.gabrielli@arm.com * neither the name of the copyright holders nor the names of its 2213955Sgiacomo.gabrielli@arm.com * contributors may be used to endorse or promote products derived from 2313955Sgiacomo.gabrielli@arm.com * this software without specific prior written permission. 2413955Sgiacomo.gabrielli@arm.com * 2513955Sgiacomo.gabrielli@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2613955Sgiacomo.gabrielli@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2713955Sgiacomo.gabrielli@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2813955Sgiacomo.gabrielli@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2913955Sgiacomo.gabrielli@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3013955Sgiacomo.gabrielli@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3113955Sgiacomo.gabrielli@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3213955Sgiacomo.gabrielli@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3313955Sgiacomo.gabrielli@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3413955Sgiacomo.gabrielli@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3513955Sgiacomo.gabrielli@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3613955Sgiacomo.gabrielli@arm.com * 3713955Sgiacomo.gabrielli@arm.com * Authors: Giacomo Gabrielli 3813955Sgiacomo.gabrielli@arm.com */ 3913955Sgiacomo.gabrielli@arm.com 4013955Sgiacomo.gabrielli@arm.com#include "arch/arm/insts/sve_mem.hh" 4113955Sgiacomo.gabrielli@arm.com 4213955Sgiacomo.gabrielli@arm.comnamespace ArmISA 4313955Sgiacomo.gabrielli@arm.com{ 4413955Sgiacomo.gabrielli@arm.com 4513955Sgiacomo.gabrielli@arm.comstd::string 4613955Sgiacomo.gabrielli@arm.comSveMemVecFillSpill::generateDisassembly(Addr pc, 4713955Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 4813955Sgiacomo.gabrielli@arm.com{ 4913955Sgiacomo.gabrielli@arm.com std::stringstream ss; 5013955Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 5113955Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 5213955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", ["); 5313955Sgiacomo.gabrielli@arm.com printIntReg(ss, base); 5413955Sgiacomo.gabrielli@arm.com if (imm != 0) { 5513955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d, mul vl", imm); 5613955Sgiacomo.gabrielli@arm.com } 5713955Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 5813955Sgiacomo.gabrielli@arm.com return ss.str(); 5913955Sgiacomo.gabrielli@arm.com} 6013955Sgiacomo.gabrielli@arm.com 6113955Sgiacomo.gabrielli@arm.comstd::string 6213955Sgiacomo.gabrielli@arm.comSveMemPredFillSpill::generateDisassembly(Addr pc, 6313955Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 6413955Sgiacomo.gabrielli@arm.com{ 6513955Sgiacomo.gabrielli@arm.com std::stringstream ss; 6613955Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 6713955Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 6813955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", ["); 6913955Sgiacomo.gabrielli@arm.com printIntReg(ss, base); 7013955Sgiacomo.gabrielli@arm.com if (imm != 0) { 7113955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d, mul vl", imm); 7213955Sgiacomo.gabrielli@arm.com } 7313955Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 7413955Sgiacomo.gabrielli@arm.com return ss.str(); 7513955Sgiacomo.gabrielli@arm.com} 7613955Sgiacomo.gabrielli@arm.com 7713955Sgiacomo.gabrielli@arm.comstd::string 7813955Sgiacomo.gabrielli@arm.comSveContigMemSS::generateDisassembly(Addr pc, const SymbolTable *symtab) const 7913955Sgiacomo.gabrielli@arm.com{ 8013955Sgiacomo.gabrielli@arm.com // TODO: add suffix to transfer register and scaling factor (LSL #<x>) 8113955Sgiacomo.gabrielli@arm.com std::stringstream ss; 8213955Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 8313955Sgiacomo.gabrielli@arm.com ccprintf(ss, "{"); 8413955Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 8513955Sgiacomo.gabrielli@arm.com ccprintf(ss, "}, "); 8613955Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 8713955Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 8813955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", ["); 8913955Sgiacomo.gabrielli@arm.com printIntReg(ss, base); 9013955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 9113955Sgiacomo.gabrielli@arm.com printIntReg(ss, offset); 9213955Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 9313955Sgiacomo.gabrielli@arm.com return ss.str(); 9413955Sgiacomo.gabrielli@arm.com} 9513955Sgiacomo.gabrielli@arm.com 9613955Sgiacomo.gabrielli@arm.comstd::string 9713955Sgiacomo.gabrielli@arm.comSveContigMemSI::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9813955Sgiacomo.gabrielli@arm.com{ 9913955Sgiacomo.gabrielli@arm.com // TODO: add suffix to transfer register 10013955Sgiacomo.gabrielli@arm.com std::stringstream ss; 10113955Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 10213955Sgiacomo.gabrielli@arm.com ccprintf(ss, "{"); 10313955Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 10413955Sgiacomo.gabrielli@arm.com ccprintf(ss, "}, "); 10513955Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 10613955Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 10713955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", ["); 10813955Sgiacomo.gabrielli@arm.com printIntReg(ss, base); 10913955Sgiacomo.gabrielli@arm.com if (imm != 0) { 11013955Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d, mul vl", imm); 11113955Sgiacomo.gabrielli@arm.com } 11213955Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 11313955Sgiacomo.gabrielli@arm.com return ss.str(); 11413955Sgiacomo.gabrielli@arm.com} 11513955Sgiacomo.gabrielli@arm.com 11613955Sgiacomo.gabrielli@arm.com} // namespace ArmISA 117