1/*
2 * Copyright (c) 2011-2013,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/mem64.hh"
41
42#include "arch/arm/tlb.hh"
43#include "base/loader/symtab.hh"
44#include "mem/request.hh"
45
46using namespace std;
47
48namespace ArmISA
49{
50
51std::string
52SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
53{
54    std::stringstream ss;
55    printMnemonic(ss, "", false);
56    ccprintf(ss, ", ");
57    printIntReg(ss, base);
58    return ss.str();
59}
60
61
62
63void
64Memory64::startDisassembly(std::ostream &os) const
65{
66    printMnemonic(os, "", false);
67    if (isDataPrefetch()||isInstPrefetch()){
68        printPFflags(os, dest);
69    }else{
70        printIntReg(os, dest);
71    }
72    ccprintf(os, ", [");
73    printIntReg(os, base);
74}
75
76void
77Memory64::setExcAcRel(bool exclusive, bool acrel)
78{
79    if (exclusive)
80        memAccessFlags |= Request::LLSC;
81    else
82        memAccessFlags |= ArmISA::TLB::AllowUnaligned;
83    if (acrel) {
84        flags[IsMemBarrier] = true;
85        flags[IsWriteBarrier] = true;
86        flags[IsReadBarrier] = true;
87    }
88}
89
90std::string
91MemoryImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
92{
93    std::stringstream ss;
94    startDisassembly(ss);
95    if (imm)
96        ccprintf(ss, ", #%d", imm);
97    ccprintf(ss, "]");
98    return ss.str();
99}
100
101std::string
102MemoryDImm64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
103{
104    std::stringstream ss;
105    printMnemonic(ss, "", false);
106    printIntReg(ss, dest);
107    ccprintf(ss, ", ");
108    printIntReg(ss, dest2);
109    ccprintf(ss, ", [");
110    printIntReg(ss, base);
111    if (imm)
112        ccprintf(ss, ", #%d", imm);
113    ccprintf(ss, "]");
114    return ss.str();
115}
116
117std::string
118MemoryDImmEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
119{
120    std::stringstream ss;
121    printMnemonic(ss, "", false);
122    printIntReg(ss, result);
123    ccprintf(ss, ", ");
124    printIntReg(ss, dest);
125    ccprintf(ss, ", ");
126    printIntReg(ss, dest2);
127    ccprintf(ss, ", [");
128    printIntReg(ss, base);
129    if (imm)
130        ccprintf(ss, ", #%d", imm);
131    ccprintf(ss, "]");
132    return ss.str();
133}
134
135std::string
136MemoryPreIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
137{
138    std::stringstream ss;
139    startDisassembly(ss);
140    ccprintf(ss, ", #%d]!", imm);
141    return ss.str();
142}
143
144std::string
145MemoryPostIndex64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
146{
147    std::stringstream ss;
148    startDisassembly(ss);
149    if (imm)
150        ccprintf(ss, "], #%d", imm);
151    ccprintf(ss, "]");
152    return ss.str();
153}
154
155std::string
156MemoryReg64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
157{
158    std::stringstream ss;
159    startDisassembly(ss);
160    printExtendOperand(false, ss, offset, type, shiftAmt);
161    ccprintf(ss, "]");
162    return ss.str();
163}
164
165std::string
166MemoryRaw64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
167{
168    std::stringstream ss;
169    startDisassembly(ss);
170    ccprintf(ss, "]");
171    return ss.str();
172}
173
174std::string
175MemoryEx64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
176{
177    std::stringstream ss;
178    printMnemonic(ss, "", false);
179    printIntReg(ss, dest);
180    ccprintf(ss, ", ");
181    printIntReg(ss, result);
182    ccprintf(ss, ", [");
183    printIntReg(ss, base);
184    ccprintf(ss, "]");
185    return ss.str();
186}
187
188std::string
189MemoryLiteral64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
190{
191    std::stringstream ss;
192    printMnemonic(ss, "", false);
193    printIntReg(ss, dest);
194    ccprintf(ss, ", #%d", pc + imm);
195    return ss.str();
196}
197}
198