1/*
2 * Copyright (c) 2015 RISC-V Foundation
3 * Copyright (c) 2017 The University of Virginia
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Alec Roelke
30 */
31
32#ifndef __ARCH_RISCV_STANDARD_INST_HH__
33#define __ARCH_RISCV_STANDARD_INST_HH__
34
35#include <string>
36
37#include "arch/riscv/insts/bitfields.hh"
38#include "arch/riscv/insts/static_inst.hh"
39#include "cpu/exec_context.hh"
40#include "cpu/static_inst.hh"
41
42namespace RiscvISA
43{
44
45/**
46 * Base class for operations that work only on registers
47 */
48class RegOp : public RiscvStaticInst
49{
50  protected:
51    using RiscvStaticInst::RiscvStaticInst;
52
53    std::string generateDisassembly(
54        Addr pc, const SymbolTable *symtab) const override;
55};
56
57/**
58 * Base class for operations with immediates (I is the type of immediate)
59 */
60template<typename I>
61class ImmOp : public RiscvStaticInst
62{
63  protected:
64    I imm;
65
66    ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
67        : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
68    {}
69};
70
71/**
72 * Base class for system operations
73 */
74class SystemOp : public RiscvStaticInst
75{
76  protected:
77    using RiscvStaticInst::RiscvStaticInst;
78
79    std::string
80    generateDisassembly(Addr pc, const SymbolTable *symtab) const override
81    {
82        return mnemonic;
83    }
84};
85
86/**
87 * Base class for CSR operations
88 */
89class CSROp : public RiscvStaticInst
90{
91  protected:
92    uint64_t csr;
93    uint64_t uimm;
94
95    /// Constructor
96    CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
97        : RiscvStaticInst(mnem, _machInst, __opClass),
98            csr(FUNCT12), uimm(CSRIMM)
99    {}
100
101    std::string generateDisassembly(
102        Addr pc, const SymbolTable *symtab) const override;
103};
104
105}
106
107#endif // __ARCH_RISCV_STANDARD_INST_HH__