Searched refs:ZeroReg (Results 1 - 17 of 17) sorted by relevance
| /gem5/src/arch/null/ |
| H A D | registers.hh | 50 const RegIndex ZeroReg = 0; member in namespace:NullISA
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| /gem5/src/arch/sparc/ |
| H A D | registers.hh | 65 const int ZeroReg = 0; // architecturally meaningful member in namespace:SparcISA
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| /gem5/src/arch/power/ |
| H A D | registers.hh | 94 const int ZeroReg = NumIntRegs - 1; member in namespace:PowerISA
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| /gem5/src/arch/x86/ |
| H A D | registers.hh | 88 const int ZeroReg = NUM_INTREGS; member in namespace:X86ISA
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| /gem5/src/arch/alpha/ |
| H A D | registers.hh | 75 const RegIndex ZeroReg = 31; // architecturally meaningful member in namespace:AlphaISA
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| H A D | ev5.cc | 90 cpu->thread->setIntReg(ZeroReg, 0);
91 cpu->thread->setFloatReg(ZeroReg, 0);
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| /gem5/src/arch/arm/ |
| H A D | registers.hh | 126 const int ZeroReg = INTREG_ZERO; member in namespace:ArmISA
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| /gem5/src/arch/mips/ |
| H A D | utility.cc | 227 cpu->thread->setIntReg(ZeroReg, 0);
228 cpu->thread->setFloatReg(ZeroReg, 0);
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| H A D | registers.hh | 110 const int ZeroReg = 0; member in namespace:MipsISA
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| /gem5/src/arch/x86/insts/ |
| H A D | static_inst.cc | 242 if (scale != 0 && index != ZeroReg)
249 if (base != ZeroReg)
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| /gem5/src/cpu/ |
| H A D | reg_class.hh | 143 return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
145 regIdx == TheISA::ZeroReg));
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| /gem5/src/cpu/minor/ |
| H A D | exec_context.hh | 101 thread.setIntReg(TheISA::ZeroReg, 0);
103 thread.setFloatReg(TheISA::ZeroReg, 0);
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| H A D | scoreboard.cc | 146 /* Use ZeroReg to mark invalid/untracked dests */
148 TheISA::ZeroReg);
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| /gem5/src/cpu/checker/ |
| H A D | cpu_impl.hh | 209 thread->setIntReg(ZeroReg, 0);
211 thread->setFloatReg(ZeroReg, 0);
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| /gem5/src/cpu/simple/ |
| H A D | base.cc | 492 thread->setIntReg(ZeroReg, 0);
494 thread->setFloatReg(ZeroReg, 0);
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| /gem5/src/cpu/o3/ |
| H A D | cpu.cc | 231 (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg;
233 commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
237 renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg,
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| /gem5/src/arch/riscv/ |
| H A D | registers.hh | 100 const int ZeroReg = 0; member in namespace:RiscvISA
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