12686Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35254Sksewell@umich.edu * All rights reserved. 42686Sksewell@umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 152686Sksewell@umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272706Sksewell@umich.edu * 285254Sksewell@umich.edu * Authors: Korey Sewell 292686Sksewell@umich.edu */ 302686Sksewell@umich.edu 3111793Sbrandon.potter@amd.com#include "arch/mips/utility.hh" 3211793Sbrandon.potter@amd.com 337678Sgblack@eecs.umich.edu#include <cmath> 347678Sgblack@eecs.umich.edu 354661Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 368799Sgblack@eecs.umich.edu#include "arch/mips/registers.hh" 378799Sgblack@eecs.umich.edu#include "arch/mips/vtophys.hh" 384661Sksewell@umich.edu#include "base/bitfield.hh" 3912334Sgabeblack@google.com#include "base/logging.hh" 408229Snate@binkert.org#include "cpu/static_inst.hh" 418229Snate@binkert.org#include "cpu/thread_context.hh" 428799Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 438229Snate@binkert.org#include "sim/serialize.hh" 442686Sksewell@umich.edu 452686Sksewell@umich.eduusing namespace MipsISA; 464661Sksewell@umich.eduusing namespace std; 472686Sksewell@umich.edu 485222Sksewell@umich.edunamespace MipsISA { 495222Sksewell@umich.edu 502686Sksewell@umich.eduuint64_t 517707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 525222Sksewell@umich.edu{ 538775Sgblack@eecs.umich.edu panic("getArgument() not implemented\n"); 545222Sksewell@umich.edu M5_DUMMY_RETURN 555222Sksewell@umich.edu} 565222Sksewell@umich.edu 575222Sksewell@umich.eduuint64_t 585222Sksewell@umich.edufpConvert(ConvertType cvt_type, double fp_val) 592686Sksewell@umich.edu{ 602686Sksewell@umich.edu 612686Sksewell@umich.edu switch (cvt_type) 622686Sksewell@umich.edu { 632686Sksewell@umich.edu case SINGLE_TO_DOUBLE: 642686Sksewell@umich.edu { 652686Sksewell@umich.edu double sdouble_val = fp_val; 662686Sksewell@umich.edu void *sdouble_ptr = &sdouble_val; 672686Sksewell@umich.edu uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; 682686Sksewell@umich.edu return sdp_bits; 692686Sksewell@umich.edu } 702686Sksewell@umich.edu 712686Sksewell@umich.edu case SINGLE_TO_WORD: 722686Sksewell@umich.edu { 732686Sksewell@umich.edu int32_t sword_val = (int32_t) fp_val; 742686Sksewell@umich.edu void *sword_ptr = &sword_val; 752686Sksewell@umich.edu uint64_t sword_bits= *(uint32_t *) sword_ptr; 762686Sksewell@umich.edu return sword_bits; 772686Sksewell@umich.edu } 782686Sksewell@umich.edu 792686Sksewell@umich.edu case WORD_TO_SINGLE: 802686Sksewell@umich.edu { 812686Sksewell@umich.edu float wfloat_val = fp_val; 822686Sksewell@umich.edu void *wfloat_ptr = &wfloat_val; 832686Sksewell@umich.edu uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; 842686Sksewell@umich.edu return wfloat_bits; 852686Sksewell@umich.edu } 862686Sksewell@umich.edu 872686Sksewell@umich.edu case WORD_TO_DOUBLE: 882686Sksewell@umich.edu { 892686Sksewell@umich.edu double wdouble_val = fp_val; 902686Sksewell@umich.edu void *wdouble_ptr = &wdouble_val; 912686Sksewell@umich.edu uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; 922686Sksewell@umich.edu return wdp_bits; 932686Sksewell@umich.edu } 942686Sksewell@umich.edu 952686Sksewell@umich.edu default: 962686Sksewell@umich.edu panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); 972686Sksewell@umich.edu return 0; 982686Sksewell@umich.edu } 992686Sksewell@umich.edu} 1002686Sksewell@umich.edu 1012686Sksewell@umich.edudouble 1025222Sksewell@umich.eduroundFP(double val, int digits) 1032686Sksewell@umich.edu{ 1042686Sksewell@umich.edu double digit_offset = pow(10.0,digits); 1052686Sksewell@umich.edu val = val * digit_offset; 1062686Sksewell@umich.edu val = val + 0.5; 1072686Sksewell@umich.edu val = floor(val); 1082686Sksewell@umich.edu val = val / digit_offset; 1092686Sksewell@umich.edu return val; 1102686Sksewell@umich.edu} 1112686Sksewell@umich.edu 1122686Sksewell@umich.edudouble 1135222Sksewell@umich.edutruncFP(double val) 1142686Sksewell@umich.edu{ 1152686Sksewell@umich.edu int trunc_val = (int) val; 1162686Sksewell@umich.edu return (double) trunc_val; 1172686Sksewell@umich.edu} 1182686Sksewell@umich.edu 1192686Sksewell@umich.edubool 1205222Sksewell@umich.edugetCondCode(uint32_t fcsr, int cc_idx) 1212686Sksewell@umich.edu{ 1222686Sksewell@umich.edu int shift = (cc_idx == 0) ? 23 : cc_idx + 24; 1232686Sksewell@umich.edu bool cc_val = (fcsr >> shift) & 0x00000001; 1242686Sksewell@umich.edu return cc_val; 1252686Sksewell@umich.edu} 1262686Sksewell@umich.edu 1272686Sksewell@umich.eduuint32_t 1285222Sksewell@umich.edugenCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) 1292686Sksewell@umich.edu{ 1302686Sksewell@umich.edu int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; 1312686Sksewell@umich.edu 1325570Snate@binkert.org fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) | 1332686Sksewell@umich.edu cc_val << cc_idx | 1342686Sksewell@umich.edu bits(fcsr, cc_idx - 1, 0); 1352686Sksewell@umich.edu 1362686Sksewell@umich.edu return fcsr; 1372686Sksewell@umich.edu} 1382686Sksewell@umich.edu 1392686Sksewell@umich.eduuint32_t 1405222Sksewell@umich.edugenInvalidVector(uint32_t fcsr_bits) 1412686Sksewell@umich.edu{ 1422686Sksewell@umich.edu //Set FCSR invalid in "flag" field 1432686Sksewell@umich.edu int invalid_offset = Invalid + Flag_Field; 1442686Sksewell@umich.edu fcsr_bits = fcsr_bits | (1 << invalid_offset); 1452686Sksewell@umich.edu 1462686Sksewell@umich.edu //Set FCSR invalid in "cause" flag 1472686Sksewell@umich.edu int cause_offset = Invalid + Cause_Field; 1482686Sksewell@umich.edu fcsr_bits = fcsr_bits | (1 << cause_offset); 1492686Sksewell@umich.edu 1502686Sksewell@umich.edu return fcsr_bits; 1512686Sksewell@umich.edu} 1522686Sksewell@umich.edu 1532686Sksewell@umich.edubool 1545222Sksewell@umich.eduisNan(void *val_ptr, int size) 1552686Sksewell@umich.edu{ 1562686Sksewell@umich.edu switch (size) 1572686Sksewell@umich.edu { 1582686Sksewell@umich.edu case 32: 1592686Sksewell@umich.edu { 1602686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 1612686Sksewell@umich.edu return (bits(val_bits, 30, 23) == 0xFF); 1622686Sksewell@umich.edu } 1632686Sksewell@umich.edu 1642686Sksewell@umich.edu case 64: 1652686Sksewell@umich.edu { 1662686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 1672686Sksewell@umich.edu return (bits(val_bits, 62, 52) == 0x7FF); 1682686Sksewell@umich.edu } 1692686Sksewell@umich.edu 1702686Sksewell@umich.edu default: 1712686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 1722686Sksewell@umich.edu } 1732686Sksewell@umich.edu} 1742686Sksewell@umich.edu 1752686Sksewell@umich.edu 1762686Sksewell@umich.edubool 1775222Sksewell@umich.eduisQnan(void *val_ptr, int size) 1782686Sksewell@umich.edu{ 1792686Sksewell@umich.edu switch (size) 1802686Sksewell@umich.edu { 1812686Sksewell@umich.edu case 32: 1822686Sksewell@umich.edu { 1832686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 1842686Sksewell@umich.edu return (bits(val_bits, 30, 22) == 0x1FE); 1852686Sksewell@umich.edu } 1862686Sksewell@umich.edu 1872686Sksewell@umich.edu case 64: 1882686Sksewell@umich.edu { 1892686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 1902686Sksewell@umich.edu return (bits(val_bits, 62, 51) == 0xFFE); 1912686Sksewell@umich.edu } 1922686Sksewell@umich.edu 1932686Sksewell@umich.edu default: 1942686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 1952686Sksewell@umich.edu } 1962686Sksewell@umich.edu} 1972686Sksewell@umich.edu 1982686Sksewell@umich.edubool 1995222Sksewell@umich.eduisSnan(void *val_ptr, int size) 2002686Sksewell@umich.edu{ 2012686Sksewell@umich.edu switch (size) 2022686Sksewell@umich.edu { 2032686Sksewell@umich.edu case 32: 2042686Sksewell@umich.edu { 2052686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 2062686Sksewell@umich.edu return (bits(val_bits, 30, 22) == 0x1FF); 2072686Sksewell@umich.edu } 2082686Sksewell@umich.edu 2092686Sksewell@umich.edu case 64: 2102686Sksewell@umich.edu { 2112686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 2122686Sksewell@umich.edu return (bits(val_bits, 62, 51) == 0xFFF); 2132686Sksewell@umich.edu } 2142686Sksewell@umich.edu 2152686Sksewell@umich.edu default: 2162686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 2172686Sksewell@umich.edu } 2182686Sksewell@umich.edu} 2194661Sksewell@umich.edu 2205222Sksewell@umich.edutemplate <class CPU> 2215222Sksewell@umich.eduvoid 2225222Sksewell@umich.eduzeroRegisters(CPU *cpu) 2235222Sksewell@umich.edu{ 2245222Sksewell@umich.edu // Insure ISA semantics 2255222Sksewell@umich.edu // (no longer very clean due to the change in setIntReg() in the 2265222Sksewell@umich.edu // cpu model. Consider changing later.) 2275222Sksewell@umich.edu cpu->thread->setIntReg(ZeroReg, 0); 22813611Sgabeblack@google.com cpu->thread->setFloatReg(ZeroReg, 0); 2295222Sksewell@umich.edu} 2305222Sksewell@umich.edu 2315222Sksewell@umich.eduvoid 2325222Sksewell@umich.edustartupCPU(ThreadContext *tc, int cpuId) 2335222Sksewell@umich.edu{ 23410407Smitch.hayenga@arm.com tc->activate(); 2355222Sksewell@umich.edu} 2365222Sksewell@umich.edu 2376329Sgblack@eecs.umich.eduvoid 2388775Sgblack@eecs.umich.eduinitCPU(ThreadContext *tc, int cpuId) 2398775Sgblack@eecs.umich.edu{} 2408775Sgblack@eecs.umich.edu 2418775Sgblack@eecs.umich.eduvoid 2426329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2436329Sgblack@eecs.umich.edu{ 24410095Sclt67@cornell.edu // First loop through the integer registers. 24510095Sclt67@cornell.edu for (int i = 0; i < NumIntRegs; i++) 24610095Sclt67@cornell.edu dest->setIntRegFlat(i, src->readIntRegFlat(i)); 24710095Sclt67@cornell.edu 24810095Sclt67@cornell.edu // Then loop through the floating point registers. 24910095Sclt67@cornell.edu for (int i = 0; i < NumFloatRegs; i++) 25013611Sgabeblack@google.com dest->setFloatRegFlat(i, src->readFloatRegFlat(i)); 25110095Sclt67@cornell.edu 25210095Sclt67@cornell.edu // Would need to add condition-code regs if implemented 25310095Sclt67@cornell.edu assert(NumCCRegs == 0); 25410095Sclt67@cornell.edu 25510095Sclt67@cornell.edu // Copy misc. registers 25610095Sclt67@cornell.edu for (int i = 0; i < NumMiscRegs; i++) 25710095Sclt67@cornell.edu dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 25810095Sclt67@cornell.edu 25910095Sclt67@cornell.edu // Copy over the PC State 26010095Sclt67@cornell.edu dest->pcState(src->pcState()); 2616329Sgblack@eecs.umich.edu} 2626329Sgblack@eecs.umich.edu 2636329Sgblack@eecs.umich.eduvoid 2646329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 2656329Sgblack@eecs.umich.edu{ 2666329Sgblack@eecs.umich.edu panic("Copy Misc. Regs Not Implemented Yet\n"); 2676329Sgblack@eecs.umich.edu} 2687693SAli.Saidi@ARM.comvoid 2697693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 2707693SAli.Saidi@ARM.com{ 27113915Sgabeblack@google.com PCState newPC = tc->pcState(); 2727720Sgblack@eecs.umich.edu newPC.set(tc->readIntReg(ReturnAddressReg)); 2737720Sgblack@eecs.umich.edu tc->pcState(newPC); 2747693SAli.Saidi@ARM.com} 2757693SAli.Saidi@ARM.com 2766329Sgblack@eecs.umich.edu 2775222Sksewell@umich.edu} // namespace MipsISA 278