Searched refs:VecPredRegContainer (Results 1 - 25 of 26) sorted by relevance

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/gem5/src/arch/null/
H A Dregisters.hh63 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/cpu/
H A Dinst_res.hh51 using VecPredRegContainer = TheISA::VecPredRegContainer;
58 VecPredRegContainer pred;
94 explicit InstResult(const VecPredRegContainer& v, const ResultType& t)
195 const VecPredRegContainer&
H A Dthread_context.hh97 using VecPredRegContainer = TheISA::VecPredRegContainer;
247 virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
249 virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
262 const VecPredRegContainer& val) = 0;
342 virtual const VecPredRegContainer &
344 virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
346 const VecPredRegContainer& val) = 0;
H A Dexec_context.hh79 using VecPredRegContainer = TheISA::VecPredRegContainer;
174 virtual const VecPredRegContainer&
178 virtual VecPredRegContainer&
184 const VecPredRegContainer& val) = 0;
H A Dsimple_thread.hh101 using VecPredRegContainer = TheISA::VecPredRegContainer;
109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
418 const VecPredRegContainer &
423 const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
429 VecPredRegContainer &
434 VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
502 setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
665 const VecPredRegContainer &
671 VecPredRegContainer
[all...]
H A Dthread_context.cc94 const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
95 const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
183 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
224 std::vector<TheISA::VecPredRegContainer> vecPredRegs(NumVecPredRegs);
/gem5/src/arch/generic/
H A Dvec_pred_reg.hh51 class VecPredRegContainer;
81 const VecPredRegContainer<NUM_BITS, Packed>,
82 VecPredRegContainer<NUM_BITS, Packed>>::type;
235 class VecPredRegContainer class
247 using MyClass = VecPredRegContainer<NumBits, Packed>;
250 VecPredRegContainer() {} function in class:VecPredRegContainer
287 operator==(const VecPredRegContainer<N2, P2>& that) const argument
295 operator!=(const VecPredRegContainer<N2, P2>& that) const argument
382 to_number(const std::string& value, VecPredRegContainer<NumBits, Packed>& p)
/gem5/src/arch/sparc/
H A Dregisters.hh60 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/cpu/o3/
H A Dregfile.hh71 using VecPredRegContainer = TheISA::VecPredRegContainer;
92 std::vector<VecPredRegContainer> vecPredRegFile;
273 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
284 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
287 return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
354 void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
H A Dthread_context.hh292 const VecPredRegContainer &
298 VecPredRegContainer&
339 const VecPredRegContainer& val) override
481 const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
482 VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
484 const VecPredRegContainer& val) override;
H A Dcpu.hh109 using VecPredRegContainer = TheISA::VecPredRegContainer;
406 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
408 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
420 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
456 const VecPredRegContainer& readArchVecPredReg(int reg_idx,
459 VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
472 void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
H A Ddyn_inst.hh72 using VecPredRegContainer = TheISA::VecPredRegContainer;
365 const VecPredRegContainer&
371 VecPredRegContainer&
418 const VecPredRegContainer& val) override
H A Dthread_context_impl.hh243 const TheISA::VecPredRegContainer&
250 TheISA::VecPredRegContainer&
303 const VecPredRegContainer& val)
H A Dcpu.cc1242 -> const VecPredRegContainer&
1251 -> VecPredRegContainer&
1300 const VecPredRegContainer& val)
1369 -> const VecPredRegContainer&
1379 -> VecPredRegContainer&
1441 FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
/gem5/src/arch/power/
H A Dregisters.hh60 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/arch/x86/
H A Dregisters.hh110 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/sim/
H A Dinsttracer.hh101 ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
208 setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
211 data.as_pred = new ::VecPredRegContainer<
/gem5/src/arch/alpha/
H A Dregisters.hh60 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/arch/arm/
H A Dregisters.hh79 using VecPredRegContainer = VecPredReg::Container;
/gem5/src/cpu/checker/
H A Dthread_context.hh328 const VecPredRegContainer &
334 VecPredRegContainer &
375 setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
536 const VecPredRegContainer &
542 VecPredRegContainer &
549 setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
H A Dcpu.hh309 const VecPredRegContainer&
317 VecPredRegContainer&
413 const VecPredRegContainer& val) override
/gem5/src/arch/mips/
H A Dregisters.hh297 using VecPredRegContainer = ::DummyVecPredRegContainer;
/gem5/src/cpu/minor/
H A Dexec_context.hh183 const TheISA::VecPredRegContainer&
191 TheISA::VecPredRegContainer&
226 const TheISA::VecPredRegContainer& val) override
/gem5/src/cpu/simple/
H A Dexec_context.hh339 const VecPredRegContainer&
348 VecPredRegContainer&
359 const VecPredRegContainer& val) override
/gem5/src/arch/riscv/
H A Dregisters.hh83 using VecPredRegContainer = ::DummyVecPredRegContainer;

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