Searched refs:TheISA (Results 26 - 50 of 125) sorted by relevance

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/gem5/src/arch/generic/
H A Dlocked_mem.hh56 namespace TheISA namespace
H A Dmemhelpers.hh69 mem = pkt->get<MemT>(TheISA::GuestByteOrder);
83 mem = TheISA::gtoh(mem);
99 mem = TheISA::htog(mem);
112 MemT host_mem = TheISA::htog(mem);
117 *(MemT *)res = TheISA::gtoh(*(MemT *)res);
119 *res = TheISA::gtoh(*res);
140 mem = TheISA::gtoh(mem);
/gem5/src/cpu/
H A Dinst_pb_trace.hh69 const StaticInstPtr si, TheISA::PCState pc,
92 StaticInstPtr si, TheISA::PCState pc, const
125 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
H A Dthread_context.hh58 namespace TheISA namespace
94 typedef TheISA::MachInst MachInst;
95 using VecRegContainer = TheISA::VecRegContainer;
96 using VecElem = TheISA::VecElem;
97 using VecPredRegContainer = TheISA::VecPredRegContainer;
143 virtual TheISA::ISA *getIsaPtr() = 0;
145 virtual TheISA::Decoder *getDecoderPtr() = 0;
266 virtual TheISA::PCState pcState() const = 0;
268 virtual void pcState(const TheISA::PCState &val) = 0;
273 TheISA
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H A Dsimple_thread.cc78 BaseTLB *_dtb, TheISA::ISA *_isa)
81 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
89 TheISA::ISA *_isa, bool use_kernel_stats)
92 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa))
113 kernelStats = new TheISA::Kernel::Statistics();
214 TheISA::copyRegs(src_tc, this);
H A Dstatic_inst.hh87 typedef TheISA::ExtMachInst ExtMachInst;
90 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
91 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
288 virtual void advancePC(TheISA::PCState &pcState) const = 0;
301 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
310 virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
316 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
317 TheISA::PCState &tgt) const;
H A Dnativetrace.hh58 const StaticInstPtr _staticInst, TheISA::PCState _pc,
82 const StaticInstPtr staticInst, TheISA::PCState pc,
H A Dexetrace.cc61 using namespace TheISA;
77 bool in_user_mode = TheISA::inUserMode(thread);
88 outs << "A" << dec << TheISA::getExecutingAsid(thread) << " ";
138 for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0;
152 for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
H A Dbase_dyn_inst.hh84 using VecRegContainer = TheISA::VecRegContainer;
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
177 TheISA::PCState pc;
201 TheISA::PCState predPC;
253 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
258 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
263 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
268 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
364 assert(TheISA
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H A Dinst_res.hh49 using VecRegContainer = TheISA::VecRegContainer;
50 using VecElem = TheISA::VecElem;
51 using VecPredRegContainer = TheISA::VecPredRegContainer;
/gem5/src/cpu/o3/
H A Dthread_context_impl.hh75 TheISA::Decoder *newDecoder = getDecoderPtr();
76 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
150 thread->kernelStats = new TheISA::Kernel::Statistics();
188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
192 TheISA::copyRegs(tc, this);
221 const TheISA::VecRegContainer&
228 TheISA::VecRegContainer&
235 const TheISA::VecElem&
243 const TheISA::VecPredRegContainer&
250 TheISA
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H A Ddyn_inst.hh67 typedef TheISA::MachInst MachInst;
69 using VecRegContainer = TheISA::VecRegContainer;
70 using VecElem = TheISA::VecElem;
71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
72 using VecPredRegContainer = TheISA::VecPredRegContainer;
75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs
82 &macroop, TheISA::PCState pc, TheISA::PCState predPC,
111 std::array<RegVal, TheISA
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H A Dfetch.hh88 typedef TheISA::MachInst MachInst;
306 bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc);
332 inline void doSquash(const TheISA::PCState &newPC,
338 void squashFromDecode(const TheISA::PCState &newPC,
354 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
381 TheISA::Decoder *decoder[Impl::MaxThreads];
387 StaticInstPtr curMacroop, TheISA::PCState thisPC,
388 TheISA::PCState nextPC, bool trace);
438 TheISA::PCState pc[Impl::MaxThreads];
H A Dcomm.hh99 TheISA::PCState pc[Impl::MaxThreads];
121 TheISA::PCState nextPC;
175 TheISA::PCState pc; // *F
/gem5/src/gpu-compute/
H A Dtlb_coalescer.cc102 TheISA::GpuTLB::TranslationState *incoming_state =
103 safe_cast<TheISA::GpuTLB::TranslationState*>(incoming_pkt->senderState);
105 TheISA::GpuTLB::TranslationState *coalesced_state =
106 safe_cast<TheISA::GpuTLB::TranslationState*>(coalesced_pkt->senderState);
111 TheISA::PageBytes);
114 TheISA::PageBytes);
144 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
149 TheISA::GpuTLB::TranslationState *sender_state =
150 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
152 TheISA
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/gem5/src/cpu/pred/
H A Dsimple_indirect.hh47 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid);
53 const TheISA::PCState& target, ThreadID tid);
75 TheISA::PCState target;
H A Dbpred_unit.hh95 TheISA::PCState &pc, ThreadID tid);
126 const TheISA::PCState &corr_target,
167 TheISA::PCState BTBLookup(Addr instPC)
192 void BTBUpdate(Addr instPC, const TheISA::PCState &target)
234 TheISA::PCState RASTarget;
/gem5/src/cpu/minor/
H A Dpipe_data.hh121 TheISA::PCState target;
129 newPredictionSeqNum(0), target(TheISA::PCState(0)),
138 TheISA::PCState target,
186 TheISA::PCState pc;
H A Ddyn_inst.hh173 TheISA::PCState pc;
187 TheISA::PCState predictedTarget;
232 RegId flatDestRegIdx[TheISA::MaxInstDestRegs];
237 pc(TheISA::PCState(0)), fault(fault_),
H A Dexec_context.hh101 thread.setIntReg(TheISA::ZeroReg, 0);
103 thread.setFloatReg(TheISA::ZeroReg, 0);
159 const TheISA::VecRegContainer &
167 TheISA::VecRegContainer &
175 TheISA::VecElem
183 const TheISA::VecPredRegContainer&
191 TheISA::VecPredRegContainer&
217 const TheISA::VecRegContainer& val) override
226 const TheISA::VecPredRegContainer& val) override
312 const TheISA
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H A Dfetch1.hh136 TheISA::PCState pc;
170 FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
243 pc(TheISA::PCState(0)),
263 TheISA::PCState pc;
/gem5/src/sim/
H A Dprocess_impl.hh49 data_ptr_swap = TheISA::htog(data_ptr);
/gem5/src/mem/
H A Dpacket_access.hh106 return TheISA::gtoh(getRaw<T>());
145 setRaw(TheISA::htog(v));
/gem5/src/arch/generic/linux/
H A Dthreadinfo.hh61 data = tc->getVirtProxy().read<T>(addr, TheISA::GuestByteOrder);
78 if (!TheISA::CurThreadInfoImplemented)
85 addr = tc->readMiscRegNoEffect(TheISA::CurThreadInfoReg);
/gem5/src/dev/alpha/
H A Dtsunami.cc50 using namespace TheISA;

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