/gem5/src/arch/generic/ |
H A D | locked_mem.hh | 56 namespace TheISA namespace
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H A D | memhelpers.hh | 69 mem = pkt->get<MemT>(TheISA::GuestByteOrder); 83 mem = TheISA::gtoh(mem); 99 mem = TheISA::htog(mem); 112 MemT host_mem = TheISA::htog(mem); 117 *(MemT *)res = TheISA::gtoh(*(MemT *)res); 119 *res = TheISA::gtoh(*res); 140 mem = TheISA::gtoh(mem);
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/gem5/src/cpu/ |
H A D | inst_pb_trace.hh | 69 const StaticInstPtr si, TheISA::PCState pc, 92 StaticInstPtr si, TheISA::PCState pc, const 125 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
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H A D | thread_context.hh | 58 namespace TheISA namespace 94 typedef TheISA::MachInst MachInst; 95 using VecRegContainer = TheISA::VecRegContainer; 96 using VecElem = TheISA::VecElem; 97 using VecPredRegContainer = TheISA::VecPredRegContainer; 143 virtual TheISA::ISA *getIsaPtr() = 0; 145 virtual TheISA::Decoder *getDecoderPtr() = 0; 266 virtual TheISA::PCState pcState() const = 0; 268 virtual void pcState(const TheISA::PCState &val) = 0; 273 TheISA [all...] |
H A D | simple_thread.cc | 78 BaseTLB *_dtb, TheISA::ISA *_isa) 81 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) 89 TheISA::ISA *_isa, bool use_kernel_stats) 92 itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(_isa)) 113 kernelStats = new TheISA::Kernel::Statistics(); 214 TheISA::copyRegs(src_tc, this);
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H A D | static_inst.hh | 87 typedef TheISA::ExtMachInst ExtMachInst; 90 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 91 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 288 virtual void advancePC(TheISA::PCState &pcState) const = 0; 301 virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const; 310 virtual TheISA::PCState branchTarget(ThreadContext *tc) const; 316 bool hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 317 TheISA::PCState &tgt) const;
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H A D | nativetrace.hh | 58 const StaticInstPtr _staticInst, TheISA::PCState _pc, 82 const StaticInstPtr staticInst, TheISA::PCState pc,
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H A D | exetrace.cc | 61 using namespace TheISA; 77 bool in_user_mode = TheISA::inUserMode(thread); 88 outs << "A" << dec << TheISA::getExecutingAsid(thread) << " "; 138 for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0; 152 for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) {
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H A D | base_dyn_inst.hh | 84 using VecRegContainer = TheISA::VecRegContainer; 98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs 177 TheISA::PCState pc; 201 TheISA::PCState predPC; 253 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 258 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx; 263 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx; 268 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx; 364 assert(TheISA [all...] |
H A D | inst_res.hh | 49 using VecRegContainer = TheISA::VecRegContainer; 50 using VecElem = TheISA::VecElem; 51 using VecPredRegContainer = TheISA::VecPredRegContainer;
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/gem5/src/cpu/o3/ |
H A D | thread_context_impl.hh | 75 TheISA::Decoder *newDecoder = getDecoderPtr(); 76 TheISA::Decoder *oldDecoder = old_context->getDecoderPtr(); 150 thread->kernelStats = new TheISA::Kernel::Statistics(); 188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState())); 192 TheISA::copyRegs(tc, this); 221 const TheISA::VecRegContainer& 228 TheISA::VecRegContainer& 235 const TheISA::VecElem& 243 const TheISA::VecPredRegContainer& 250 TheISA [all...] |
H A D | dyn_inst.hh | 67 typedef TheISA::MachInst MachInst; 69 using VecRegContainer = TheISA::VecRegContainer; 70 using VecElem = TheISA::VecElem; 71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; 72 using VecPredRegContainer = TheISA::VecPredRegContainer; 75 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 76 MaxInstDestRegs = TheISA::MaxInstDestRegs //< Max dest regs 82 ¯oop, TheISA::PCState pc, TheISA::PCState predPC, 111 std::array<RegVal, TheISA [all...] |
H A D | fetch.hh | 88 typedef TheISA::MachInst MachInst; 306 bool lookupAndUpdateNextPC(const DynInstPtr &inst, TheISA::PCState &pc); 332 inline void doSquash(const TheISA::PCState &newPC, 338 void squashFromDecode(const TheISA::PCState &newPC, 354 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 381 TheISA::Decoder *decoder[Impl::MaxThreads]; 387 StaticInstPtr curMacroop, TheISA::PCState thisPC, 388 TheISA::PCState nextPC, bool trace); 438 TheISA::PCState pc[Impl::MaxThreads];
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H A D | comm.hh | 99 TheISA::PCState pc[Impl::MaxThreads]; 121 TheISA::PCState nextPC; 175 TheISA::PCState pc; // *F
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/gem5/src/gpu-compute/ |
H A D | tlb_coalescer.cc | 102 TheISA::GpuTLB::TranslationState *incoming_state = 103 safe_cast<TheISA::GpuTLB::TranslationState*>(incoming_pkt->senderState); 105 TheISA::GpuTLB::TranslationState *coalesced_state = 106 safe_cast<TheISA::GpuTLB::TranslationState*>(coalesced_pkt->senderState); 111 TheISA::PageBytes); 114 TheISA::PageBytes); 144 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes); 149 TheISA::GpuTLB::TranslationState *sender_state = 150 safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 152 TheISA [all...] |
/gem5/src/cpu/pred/ |
H A D | simple_indirect.hh | 47 bool lookup(Addr br_addr, TheISA::PCState& br_target, ThreadID tid); 53 const TheISA::PCState& target, ThreadID tid); 75 TheISA::PCState target;
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H A D | bpred_unit.hh | 95 TheISA::PCState &pc, ThreadID tid); 126 const TheISA::PCState &corr_target, 167 TheISA::PCState BTBLookup(Addr instPC) 192 void BTBUpdate(Addr instPC, const TheISA::PCState &target) 234 TheISA::PCState RASTarget;
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/gem5/src/cpu/minor/ |
H A D | pipe_data.hh | 121 TheISA::PCState target; 129 newPredictionSeqNum(0), target(TheISA::PCState(0)), 138 TheISA::PCState target, 186 TheISA::PCState pc;
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H A D | dyn_inst.hh | 173 TheISA::PCState pc; 187 TheISA::PCState predictedTarget; 232 RegId flatDestRegIdx[TheISA::MaxInstDestRegs]; 237 pc(TheISA::PCState(0)), fault(fault_),
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H A D | exec_context.hh | 101 thread.setIntReg(TheISA::ZeroReg, 0); 103 thread.setFloatReg(TheISA::ZeroReg, 0); 159 const TheISA::VecRegContainer & 167 TheISA::VecRegContainer & 175 TheISA::VecElem 183 const TheISA::VecPredRegContainer& 191 TheISA::VecPredRegContainer& 217 const TheISA::VecRegContainer& val) override 226 const TheISA::VecPredRegContainer& val) override 312 const TheISA [all...] |
H A D | fetch1.hh | 136 TheISA::PCState pc; 170 FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) : 243 pc(TheISA::PCState(0)), 263 TheISA::PCState pc;
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/gem5/src/sim/ |
H A D | process_impl.hh | 49 data_ptr_swap = TheISA::htog(data_ptr);
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/gem5/src/mem/ |
H A D | packet_access.hh | 106 return TheISA::gtoh(getRaw<T>()); 145 setRaw(TheISA::htog(v));
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/gem5/src/arch/generic/linux/ |
H A D | threadinfo.hh | 61 data = tc->getVirtProxy().read<T>(addr, TheISA::GuestByteOrder); 78 if (!TheISA::CurThreadInfoImplemented) 85 addr = tc->readMiscRegNoEffect(TheISA::CurThreadInfoReg);
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/gem5/src/dev/alpha/ |
H A D | tsunami.cc | 50 using namespace TheISA;
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