11689SN/A/* 213610Sgiacomo.gabrielli@arm.com * Copyright (c) 2011, 2016-2017 ARM Limited 310239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 48137SAli.Saidi@ARM.com * All rights reserved 58137SAli.Saidi@ARM.com * 68137SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 78137SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 88137SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 98137SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 108137SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 118137SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 128137SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 138137SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 148137SAli.Saidi@ARM.com * 152329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 4212105Snathanael.premillieu@arm.com * Nathanael Premillieu 431689SN/A */ 441689SN/A 452292SN/A#ifndef __CPU_O3_COMM_HH__ 462292SN/A#define __CPU_O3_COMM_HH__ 471060SN/A 481061SN/A#include <vector> 491684SN/A 507720Sgblack@eecs.umich.edu#include "arch/types.hh" 516216Snate@binkert.org#include "base/types.hh" 526216Snate@binkert.org#include "cpu/inst_seq.hh" 532980Sgblack@eecs.umich.edu#include "sim/faults.hh" 541060SN/A 552348SN/A/** Struct that defines the information passed from fetch to decode. */ 561060SN/Atemplate<class Impl> 572292SN/Astruct DefaultFetchDefaultDecode { 582292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 592292SN/A 602292SN/A int size; 612292SN/A 622292SN/A DynInstPtr insts[Impl::MaxWidth]; 632292SN/A Fault fetchFault; 642292SN/A InstSeqNum fetchFaultSN; 652292SN/A bool clearFetchFault; 662292SN/A}; 672292SN/A 682348SN/A/** Struct that defines the information passed from decode to rename. */ 692292SN/Atemplate<class Impl> 702292SN/Astruct DefaultDecodeDefaultRename { 711061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 721061SN/A 731061SN/A int size; 741061SN/A 751461SN/A DynInstPtr insts[Impl::MaxWidth]; 761060SN/A}; 771060SN/A 782348SN/A/** Struct that defines the information passed from rename to IEW. */ 791060SN/Atemplate<class Impl> 802292SN/Astruct DefaultRenameDefaultIEW { 811061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 821061SN/A 831061SN/A int size; 841061SN/A 851461SN/A DynInstPtr insts[Impl::MaxWidth]; 861060SN/A}; 871060SN/A 882348SN/A/** Struct that defines the information passed from IEW to commit. */ 891060SN/Atemplate<class Impl> 902292SN/Astruct DefaultIEWDefaultCommit { 911061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 921061SN/A 931061SN/A int size; 941061SN/A 951461SN/A DynInstPtr insts[Impl::MaxWidth]; 969046SAli.Saidi@ARM.com DynInstPtr mispredictInst[Impl::MaxThreads]; 979046SAli.Saidi@ARM.com Addr mispredPC[Impl::MaxThreads]; 989046SAli.Saidi@ARM.com InstSeqNum squashedSeqNum[Impl::MaxThreads]; 999046SAli.Saidi@ARM.com TheISA::PCState pc[Impl::MaxThreads]; 1001062SN/A 1012292SN/A bool squash[Impl::MaxThreads]; 1022292SN/A bool branchMispredict[Impl::MaxThreads]; 1032292SN/A bool branchTaken[Impl::MaxThreads]; 1042292SN/A bool includeSquashInst[Impl::MaxThreads]; 1051060SN/A}; 1061060SN/A 1071060SN/Atemplate<class Impl> 1081060SN/Astruct IssueStruct { 1091061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 1101061SN/A 1111061SN/A int size; 1121061SN/A 1131461SN/A DynInstPtr insts[Impl::MaxWidth]; 1141060SN/A}; 1151060SN/A 1162348SN/A/** Struct that defines all backwards communication. */ 1172292SN/Atemplate<class Impl> 1181060SN/Astruct TimeBufStruct { 1197851SMatt.Horsnell@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 1201060SN/A struct decodeComm { 1219260SAli.Saidi@ARM.com TheISA::PCState nextPC; 1229046SAli.Saidi@ARM.com DynInstPtr mispredictInst; 1239046SAli.Saidi@ARM.com DynInstPtr squashInst; 1249260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; 1259046SAli.Saidi@ARM.com Addr mispredPC; 1269260SAli.Saidi@ARM.com uint64_t branchAddr; 1279046SAli.Saidi@ARM.com unsigned branchCount; 1281060SN/A bool squash; 1291060SN/A bool predIncorrect; 1301061SN/A bool branchMispredict; 1311061SN/A bool branchTaken; 1321060SN/A }; 1331060SN/A 1342292SN/A decodeComm decodeInfo[Impl::MaxThreads]; 1351060SN/A 1361060SN/A struct renameComm { 1371060SN/A }; 1381060SN/A 1392292SN/A renameComm renameInfo[Impl::MaxThreads]; 1401060SN/A 1411060SN/A struct iewComm { 1422292SN/A // Also eventually include skid buffer space. 1432292SN/A unsigned freeIQEntries; 14410239Sbinhpham@cs.rutgers.edu unsigned freeLQEntries; 14510239Sbinhpham@cs.rutgers.edu unsigned freeSQEntries; 14610239Sbinhpham@cs.rutgers.edu unsigned dispatchedToLQ; 14710239Sbinhpham@cs.rutgers.edu unsigned dispatchedToSQ; 1481060SN/A 1492292SN/A unsigned iqCount; 1502292SN/A unsigned ldstqCount; 1512292SN/A 1522292SN/A unsigned dispatched; 1539260SAli.Saidi@ARM.com bool usedIQ; 1549260SAli.Saidi@ARM.com bool usedLSQ; 1551060SN/A }; 1561060SN/A 1572292SN/A iewComm iewInfo[Impl::MaxThreads]; 1581060SN/A 1591060SN/A struct commitComm { 1609260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 1619260SAli.Saidi@ARM.com // This code has been re-structured for better packing of variables 1629260SAli.Saidi@ARM.com // instead of by stage which is the more logical way to arrange the 1639260SAli.Saidi@ARM.com // data. 1649260SAli.Saidi@ARM.com // F = Fetch 1659260SAli.Saidi@ARM.com // D = Decode 1669260SAli.Saidi@ARM.com // I = IEW 1679260SAli.Saidi@ARM.com // R = Rename 1689260SAli.Saidi@ARM.com // As such each member is annotated with who consumes it 1699260SAli.Saidi@ARM.com // e.g. bool variable name // *F,R for Fetch and Rename 1709260SAli.Saidi@ARM.com ///////////////////////////////////////////////////////////////////// 1712292SN/A 1729260SAli.Saidi@ARM.com /// The pc of the next instruction to execute. This is the next 1739260SAli.Saidi@ARM.com /// instruction for a branch mispredict, but the same instruction for 1749260SAli.Saidi@ARM.com /// order violation and the like 1759260SAli.Saidi@ARM.com TheISA::PCState pc; // *F 1761060SN/A 1779260SAli.Saidi@ARM.com /// Provide fetch the instruction that mispredicted, if this 1789260SAli.Saidi@ARM.com /// pointer is not-null a misprediction occured 1799260SAli.Saidi@ARM.com DynInstPtr mispredictInst; // *F 1801061SN/A 1819260SAli.Saidi@ARM.com /// Instruction that caused the a non-mispredict squash 1829260SAli.Saidi@ARM.com DynInstPtr squashInst; // *F 1831061SN/A 18410824SAndreas.Sandberg@ARM.com /// Hack for now to send back a strictly ordered access to the 18510824SAndreas.Sandberg@ARM.com /// IEW stage. 18610824SAndreas.Sandberg@ARM.com DynInstPtr strictlyOrderedLoad; // *I 1878137SAli.Saidi@ARM.com 1889260SAli.Saidi@ARM.com /// Communication specifically to the IQ to tell the IQ that it can 1899260SAli.Saidi@ARM.com /// schedule a non-speculative instruction. 1909260SAli.Saidi@ARM.com InstSeqNum nonSpecSeqNum; // *I 1918137SAli.Saidi@ARM.com 1929260SAli.Saidi@ARM.com /// Represents the instruction that has either been retired or 1939260SAli.Saidi@ARM.com /// squashed. Similar to having a single bus that broadcasts the 1949260SAli.Saidi@ARM.com /// retired or squashed sequence number. 1959260SAli.Saidi@ARM.com InstSeqNum doneSeqNum; // *F, I 1968137SAli.Saidi@ARM.com 1979260SAli.Saidi@ARM.com /// Tell Rename how many free entries it has in the ROB 1989260SAli.Saidi@ARM.com unsigned freeROBEntries; // *R 1992292SN/A 2009260SAli.Saidi@ARM.com bool squash; // *F, D, R, I 2019260SAli.Saidi@ARM.com bool robSquashing; // *F, D, R, I 2029260SAli.Saidi@ARM.com 2039260SAli.Saidi@ARM.com /// Rename should re-read number of free rob entries 2049260SAli.Saidi@ARM.com bool usedROB; // *R 2059260SAli.Saidi@ARM.com 2069260SAli.Saidi@ARM.com /// Notify Rename that the ROB is empty 2079260SAli.Saidi@ARM.com bool emptyROB; // *R 2089260SAli.Saidi@ARM.com 2099260SAli.Saidi@ARM.com /// Was the branch taken or not 2109260SAli.Saidi@ARM.com bool branchTaken; // *F 2119260SAli.Saidi@ARM.com /// If an interrupt is pending and fetch should stall 2129260SAli.Saidi@ARM.com bool interruptPending; // *F 2139260SAli.Saidi@ARM.com /// If the interrupt ended up being cleared before being handled 2149260SAli.Saidi@ARM.com bool clearInterrupt; // *F 2159260SAli.Saidi@ARM.com 21610824SAndreas.Sandberg@ARM.com /// Hack for now to send back an strictly ordered access to 21710824SAndreas.Sandberg@ARM.com /// the IEW stage. 21810824SAndreas.Sandberg@ARM.com bool strictlyOrdered; // *I 2192292SN/A 2201060SN/A }; 2211060SN/A 2222292SN/A commitComm commitInfo[Impl::MaxThreads]; 2232292SN/A 2242292SN/A bool decodeBlock[Impl::MaxThreads]; 2252292SN/A bool decodeUnblock[Impl::MaxThreads]; 2262292SN/A bool renameBlock[Impl::MaxThreads]; 2272292SN/A bool renameUnblock[Impl::MaxThreads]; 2282292SN/A bool iewBlock[Impl::MaxThreads]; 2292292SN/A bool iewUnblock[Impl::MaxThreads]; 2301060SN/A}; 2311060SN/A 2322292SN/A#endif //__CPU_O3_COMM_HH__ 233