1/*
2 * Copyright (c) 2011, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Nathanael Premillieu
43 */
44
45#ifndef __CPU_O3_COMM_HH__
46#define __CPU_O3_COMM_HH__
47
48#include <vector>
49
50#include "arch/types.hh"
51#include "base/types.hh"
52#include "cpu/inst_seq.hh"
53#include "sim/faults.hh"
54
55/** Struct that defines the information passed from fetch to decode. */
56template<class Impl>
57struct DefaultFetchDefaultDecode {
58    typedef typename Impl::DynInstPtr DynInstPtr;
59
60    int size;
61
62    DynInstPtr insts[Impl::MaxWidth];
63    Fault fetchFault;
64    InstSeqNum fetchFaultSN;
65    bool clearFetchFault;
66};
67
68/** Struct that defines the information passed from decode to rename. */
69template<class Impl>
70struct DefaultDecodeDefaultRename {
71    typedef typename Impl::DynInstPtr DynInstPtr;
72
73    int size;
74
75    DynInstPtr insts[Impl::MaxWidth];
76};
77
78/** Struct that defines the information passed from rename to IEW. */
79template<class Impl>
80struct DefaultRenameDefaultIEW {
81    typedef typename Impl::DynInstPtr DynInstPtr;
82
83    int size;
84
85    DynInstPtr insts[Impl::MaxWidth];
86};
87
88/** Struct that defines the information passed from IEW to commit. */
89template<class Impl>
90struct DefaultIEWDefaultCommit {
91    typedef typename Impl::DynInstPtr DynInstPtr;
92
93    int size;
94
95    DynInstPtr insts[Impl::MaxWidth];
96    DynInstPtr mispredictInst[Impl::MaxThreads];
97    Addr mispredPC[Impl::MaxThreads];
98    InstSeqNum squashedSeqNum[Impl::MaxThreads];
99    TheISA::PCState pc[Impl::MaxThreads];
100
101    bool squash[Impl::MaxThreads];
102    bool branchMispredict[Impl::MaxThreads];
103    bool branchTaken[Impl::MaxThreads];
104    bool includeSquashInst[Impl::MaxThreads];
105};
106
107template<class Impl>
108struct IssueStruct {
109    typedef typename Impl::DynInstPtr DynInstPtr;
110
111    int size;
112
113    DynInstPtr insts[Impl::MaxWidth];
114};
115
116/** Struct that defines all backwards communication. */
117template<class Impl>
118struct TimeBufStruct {
119    typedef typename Impl::DynInstPtr DynInstPtr;
120    struct decodeComm {
121        TheISA::PCState nextPC;
122        DynInstPtr mispredictInst;
123        DynInstPtr squashInst;
124        InstSeqNum doneSeqNum;
125        Addr mispredPC;
126        uint64_t branchAddr;
127        unsigned branchCount;
128        bool squash;
129        bool predIncorrect;
130        bool branchMispredict;
131        bool branchTaken;
132    };
133
134    decodeComm decodeInfo[Impl::MaxThreads];
135
136    struct renameComm {
137    };
138
139    renameComm renameInfo[Impl::MaxThreads];
140
141    struct iewComm {
142        // Also eventually include skid buffer space.
143        unsigned freeIQEntries;
144        unsigned freeLQEntries;
145        unsigned freeSQEntries;
146        unsigned dispatchedToLQ;
147        unsigned dispatchedToSQ;
148
149        unsigned iqCount;
150        unsigned ldstqCount;
151
152        unsigned dispatched;
153        bool usedIQ;
154        bool usedLSQ;
155    };
156
157    iewComm iewInfo[Impl::MaxThreads];
158
159    struct commitComm {
160        /////////////////////////////////////////////////////////////////////
161        // This code has been re-structured for better packing of variables
162        // instead of by stage which is the more logical way to arrange the
163        // data.
164        // F = Fetch
165        // D = Decode
166        // I = IEW
167        // R = Rename
168        // As such each member is annotated with who consumes it
169        // e.g. bool variable name // *F,R for Fetch and Rename
170        /////////////////////////////////////////////////////////////////////
171
172        /// The pc of the next instruction to execute. This is the next
173        /// instruction for a branch mispredict, but the same instruction for
174        /// order violation and the like
175        TheISA::PCState pc; // *F
176
177        /// Provide fetch the instruction that mispredicted, if this
178        /// pointer is not-null a misprediction occured
179        DynInstPtr mispredictInst;  // *F
180
181        /// Instruction that caused the a non-mispredict squash
182        DynInstPtr squashInst; // *F
183
184        /// Hack for now to send back a strictly ordered access to the
185        /// IEW stage.
186        DynInstPtr strictlyOrderedLoad; // *I
187
188        /// Communication specifically to the IQ to tell the IQ that it can
189        /// schedule a non-speculative instruction.
190        InstSeqNum nonSpecSeqNum; // *I
191
192        /// Represents the instruction that has either been retired or
193        /// squashed.  Similar to having a single bus that broadcasts the
194        /// retired or squashed sequence number.
195        InstSeqNum doneSeqNum; // *F, I
196
197        /// Tell Rename how many free entries it has in the ROB
198        unsigned freeROBEntries; // *R
199
200        bool squash; // *F, D, R, I
201        bool robSquashing; // *F, D, R, I
202
203        /// Rename should re-read number of free rob entries
204        bool usedROB; // *R
205
206        /// Notify Rename that the ROB is empty
207        bool emptyROB; // *R
208
209        /// Was the branch taken or not
210        bool branchTaken; // *F
211        /// If an interrupt is pending and fetch should stall
212        bool interruptPending; // *F
213        /// If the interrupt ended up being cleared before being handled
214        bool clearInterrupt; // *F
215
216        /// Hack for now to send back an strictly ordered access to
217        /// the IEW stage.
218        bool strictlyOrdered; // *I
219
220    };
221
222    commitComm commitInfo[Impl::MaxThreads];
223
224    bool decodeBlock[Impl::MaxThreads];
225    bool decodeUnblock[Impl::MaxThreads];
226    bool renameBlock[Impl::MaxThreads];
227    bool renameUnblock[Impl::MaxThreads];
228    bool iewBlock[Impl::MaxThreads];
229    bool iewUnblock[Impl::MaxThreads];
230};
231
232#endif //__CPU_O3_COMM_HH__
233