Searched hist:9920 (Results 1 - 25 of 50) sorted by relevance
| /gem5/src/arch/power/insts/ | ||
| H A D | static_inst.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/cpu/ | ||
| H A D | reg_class.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | reg_class.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | thread_context.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/cpu/o3/ | ||
| H A D | free_list.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | regfile.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | rename_map.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | free_list.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | rename_map.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/x86/insts/ | ||
| H A D | static_inst.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/null/ | ||
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/alpha/ | ||
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | isa.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | utility.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/power/ | ||
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | isa.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | utility.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/sparc/ | ||
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | isa.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | utility.cc | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/mips/ | ||
| H A D | isa.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/x86/ | ||
| H A D | isa.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
| /gem5/src/arch/arm/ | ||
| H A D | registers.hh | diff 9920:028e4da64b42 Tue Oct 15 14:22:00 EDT 2013 Yasuko Eckert <yasuko.eckert@amd.com> cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. |
Completed in 135 milliseconds