Searched hist:247 (Results 26 - 50 of 50) sorted by relevance

12

/gem5/src/arch/x86/
H A Dpagetable_walker.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/arch/arm/
H A Dtable_walker.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dtable_walker.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Disa.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/cpu/checker/
H A Dcpu.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dcpu.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/mem/
H A Dport.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Drequest.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dpacket.hhdiff 13350:247e4108a5e8 Mon Oct 10 09:40:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/dev/
H A Dio_device.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dio_device.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/mem/ruby/system/
H A DRubyPort.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/mem/cache/
H A Dcache.hhdiff 13350:247e4108a5e8 Mon Oct 10 09:40:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dcache.ccdiff 13350:247e4108a5e8 Mon Oct 10 09:40:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbase.hhdiff 13350:247e4108a5e8 Mon Oct 10 09:40:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbase.ccdiff 13350:247e4108a5e8 Mon Oct 10 09:40:00 EDT 2016 Nikos Nikoleris <nikos.nikoleris@arm.com> mem: Restructure whole-line writes to simplify write merging

This patch changes how we deal with whole-line writes their
responses. With these changes, we use the MSHR tracking to determine
if a whole-line is written, and on a fill we simply handle the
invalidation response, with the actual writes taking place as part of
satisfying the CPU-side hit.

Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b
Reviewed-on: https://gem5-review.googlesource.com/c/12905
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/sim/
H A Dsystem.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dsystem.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/cpu/simple/
H A Dbase.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dtiming.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Datomic.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/cpu/
H A Dbase.ccdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dbase.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
H A Dbase_dyn_inst.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/cpu/o3/
H A Dfetch_impl.hhdiff 8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.

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