1/*
2 * Copyright (c) 2011,2013,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Geoffrey Blake
42 */
43
44#include "cpu/checker/cpu.hh"
45
46#include <list>
47#include <string>
48
49#include "arch/generic/tlb.hh"
50#include "arch/vtophys.hh"
51#include "cpu/base.hh"
52#include "cpu/simple_thread.hh"
53#include "cpu/static_inst.hh"
54#include "cpu/thread_context.hh"
55#include "cpu/utils.hh"
56#include "params/CheckerCPU.hh"
57#include "sim/full_system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62void
63CheckerCPU::init()
64{
65    masterId = systemPtr->getMasterId(this);
66}
67
68CheckerCPU::CheckerCPU(Params *p)
69    : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
70      tc(NULL), thread(NULL),
71      unverifiedReq(nullptr),
72      unverifiedMemData(nullptr)
73{
74    curStaticInst = NULL;
75    curMacroStaticInst = NULL;
76
77    numInst = 0;
78    startNumInst = 0;
79    numLoad = 0;
80    startNumLoad = 0;
81    youngestSN = 0;
82
83    changedPC = willChangePC = false;
84
85    exitOnError = p->exitOnError;
86    warnOnlyOnLoadError = p->warnOnlyOnLoadError;
87    itb = p->itb;
88    dtb = p->dtb;
89    workload = p->workload;
90
91    updateOnError = true;
92}
93
94CheckerCPU::~CheckerCPU()
95{
96}
97
98void
99CheckerCPU::setSystem(System *system)
100{
101    const Params *p(dynamic_cast<const Params *>(_params));
102
103    systemPtr = system;
104
105    if (FullSystem) {
106        thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
107                                  p->isa[0], false);
108    } else {
109        thread = new SimpleThread(this, 0, systemPtr,
110                                  workload.size() ? workload[0] : NULL,
111                                  itb, dtb, p->isa[0]);
112    }
113
114    tc = thread->getTC();
115    threadContexts.push_back(tc);
116    thread->kernelStats = NULL;
117    // Thread should never be null after this
118    assert(thread != NULL);
119}
120
121void
122CheckerCPU::setIcachePort(MasterPort *icache_port)
123{
124    icachePort = icache_port;
125}
126
127void
128CheckerCPU::setDcachePort(MasterPort *dcache_port)
129{
130    dcachePort = dcache_port;
131}
132
133void
134CheckerCPU::serialize(ostream &os) const
135{
136}
137
138void
139CheckerCPU::unserialize(CheckpointIn &cp)
140{
141}
142
143RequestPtr
144CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size,
145                                  Request::Flags flags,
146                                  const std::vector<bool>& byte_enable,
147                                  int& frag_size, int& size_left) const
148{
149    frag_size = std::min(
150        cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()),
151        (Addr) size_left);
152    size_left -= frag_size;
153
154    RequestPtr mem_req;
155
156    if (!byte_enable.empty()) {
157        // Set up byte-enable mask for the current fragment
158        auto it_start = byte_enable.cbegin() + (size - (frag_size +
159                                                        size_left));
160        auto it_end = byte_enable.cbegin() + (size - size_left);
161        if (isAnyActiveElement(it_start, it_end)) {
162            mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
163                    flags, masterId, thread->pcState().instAddr(),
164                    tc->contextId());
165            mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
166        }
167    } else {
168        mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
169                    flags, masterId, thread->pcState().instAddr(),
170                    tc->contextId());
171    }
172
173    return mem_req;
174}
175
176Fault
177CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
178                    Request::Flags flags,
179                    const std::vector<bool>& byteEnable)
180{
181    Fault fault = NoFault;
182    bool checked_flags = false;
183    bool flags_match = true;
184    Addr pAddr = 0x0;
185
186    Addr frag_addr = addr;
187    int frag_size = 0;
188    int size_left = size;
189    bool predicate;
190
191    // Need to account for multiple accesses like the Atomic and TimingSimple
192    while (1) {
193        RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
194                                                   byteEnable, frag_size,
195                                                   size_left);
196
197        predicate = (mem_req != nullptr);
198
199        // translate to physical address
200        if (predicate) {
201            fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
202        }
203
204        if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
205            flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
206                                     mem_req->getPaddr(), mem_req->getFlags());
207            pAddr = mem_req->getPaddr();
208            checked_flags = true;
209        }
210
211        // Now do the access
212        if (predicate && fault == NoFault &&
213            !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
214            PacketPtr pkt = Packet::createRead(mem_req);
215
216            pkt->dataStatic(data);
217
218            if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
219                // Access memory to see if we have the same data
220                dcachePort->sendFunctional(pkt);
221            } else {
222                // Assume the data is correct if it's an uncached access
223                memcpy(data, unverifiedMemData, frag_size);
224            }
225
226            delete pkt;
227        }
228
229        if (fault != NoFault) {
230            if (mem_req->isPrefetch()) {
231                fault = NoFault;
232            }
233            break;
234        }
235
236        //If we don't need to access a second cache line, stop now.
237        if (size_left == 0)
238        {
239            break;
240        }
241
242        // Setup for accessing next cache line
243        frag_addr += frag_size;
244        data += frag_size;
245        unverifiedMemData += frag_size;
246    }
247
248    if (!flags_match) {
249        warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
250             curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
251             unverifiedReq->getFlags(), frag_addr, pAddr, flags);
252        handleError();
253    }
254
255    return fault;
256}
257
258Fault
259CheckerCPU::writeMem(uint8_t *data, unsigned size,
260                     Addr addr, Request::Flags flags, uint64_t *res,
261                     const std::vector<bool>& byteEnable)
262{
263    assert(byteEnable.empty() || byteEnable.size() == size);
264
265    Fault fault = NoFault;
266    bool checked_flags = false;
267    bool flags_match = true;
268    Addr pAddr = 0x0;
269    static uint8_t zero_data[64] = {};
270
271    Addr frag_addr = addr;
272    int frag_size = 0;
273    int size_left = size;
274    bool predicate;
275
276    // Need to account for a multiple access like Atomic and Timing CPUs
277    while (1) {
278        RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
279                                                   byteEnable, frag_size,
280                                                   size_left);
281
282        predicate = (mem_req != nullptr);
283
284        if (predicate) {
285            fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
286        }
287
288        if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
289           flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
290                                    mem_req->getPaddr(), mem_req->getFlags());
291           pAddr = mem_req->getPaddr();
292           checked_flags = true;
293        }
294
295        /*
296         * We don't actually check memory for the store because there
297         * is no guarantee it has left the lsq yet, and therefore we
298         * can't verify the memory on stores without lsq snooping
299         * enabled.  This is left as future work for the Checker: LSQ snooping
300         * and memory validation after stores have committed.
301         */
302        bool was_prefetch = mem_req->isPrefetch();
303
304        //If we don't need to access a second cache line, stop now.
305        if (fault != NoFault || size_left == 0)
306        {
307            if (fault != NoFault && was_prefetch) {
308              fault = NoFault;
309            }
310            break;
311        }
312
313        frag_addr += frag_size;
314   }
315
316   if (!flags_match) {
317       warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
318            curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
319            unverifiedReq->getFlags(), frag_addr, pAddr, flags);
320       handleError();
321   }
322
323   // Assume the result was the same as the one passed in.  This checker
324   // doesn't check if the SC should succeed or fail, it just checks the
325   // value.
326   if (unverifiedReq && res && unverifiedReq->extraDataValid())
327       *res = unverifiedReq->getExtraData();
328
329   // Entire purpose here is to make sure we are getting the
330   // same data to send to the mem system as the CPU did.
331   // Cannot check this is actually what went to memory because
332   // there stores can be in ld/st queue or coherent operations
333   // overwriting values.
334   bool extraData = false;
335   if (unverifiedReq) {
336       extraData = unverifiedReq->extraDataValid() ?
337                        unverifiedReq->getExtraData() : true;
338   }
339
340   // If the request is to ZERO a cache block, there is no data to check
341   // against, but it's all zero. We need something to compare to, so use a
342   // const set of zeros.
343   if (flags & Request::STORE_NO_DATA) {
344       assert(!data);
345       assert(sizeof(zero_data) <= size);
346       data = zero_data;
347   }
348
349   if (unverifiedReq && unverifiedMemData &&
350       memcmp(data, unverifiedMemData, size) && extraData) {
351           warn("%lli: Store value does not match value sent to memory! "
352                  "data: %#x inst_data: %#x", curTick(), data,
353                  unverifiedMemData);
354       handleError();
355   }
356
357   return fault;
358}
359
360Addr
361CheckerCPU::dbg_vtophys(Addr addr)
362{
363    return vtophys(tc, addr);
364}
365
366/**
367 * Checks if the flags set by the Checker and Checkee match.
368 */
369bool
370CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
371                       Addr pAddr, int flags)
372{
373    Addr unverifiedVAddr = unverified_req->getVaddr();
374    Addr unverifiedPAddr = unverified_req->getPaddr();
375    int unverifiedFlags = unverified_req->getFlags();
376
377    if (unverifiedVAddr != vAddr ||
378        unverifiedPAddr != pAddr ||
379        unverifiedFlags != flags) {
380        return false;
381    }
382
383    return true;
384}
385
386void
387CheckerCPU::dumpAndExit()
388{
389    warn("%lli: Checker PC:%s",
390         curTick(), thread->pcState());
391    panic("Checker found an error!");
392}
393