Searched hist:2008 (Results 451 - 475 of 494) sorted by relevance

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/gem5/src/sim/
H A Dserialize.hhdiff 5739:27c1d1048c65 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> clean: Move some stuff from the hh file to the cc file.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
H A Dmain.ccdiff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5.

This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack. This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name. Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things. Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
/gem5/src/arch/mips/isa/
H A Ddecoder.isadiff 5585:45233156c3cc Mon Oct 06 02:07:00 EDT 2008 Korey Sewell <ksewell@umich.edu> fix shadow set bugs in MIPS code that caused out of bounds access...
panic rdpgpr/wrpgpr instructions until a better impl.
of MIPS shadow sets is available.
diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
/gem5/src/arch/sparc/
H A Dtlb.hhdiff 5555:07c10d7dd62d Tue Sep 23 23:38:00 EDT 2008 Nathan Binkert <nate@binkert.org> sparc: Fix style, create a helper function for translation.
The translate function simplifies code and removes some compiler
warnings in gcc 3.4
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
H A Dvtophys.ccdiff 5560:c2db27fc4f27 Fri Sep 26 11:18:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: bring this file into M5 style, use the new pte translate function.
/gem5/src/cpu/o3/
H A Dregfile.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
H A Dcommit_impl.hhdiff 5769:e53bdd0e4bf1 Sat Dec 06 17:18:00 EST 2008 Nathan Binkert <nate@binkert.org> eventq: use the flags data structure
diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5557:03c186e416aa Fri Sep 26 10:44:00 EDT 2008 Kevin Lim <ktlim@umich.edu> O3CPU: Fix thread writeback logic.
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
H A DO3CPU.pydiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
H A Ddecode.hhdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
H A Drename.hhdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
H A Dmem_dep_unit_impl.hhdiff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
/gem5/src/python/m5/
H A Dsimulate.pydiff 5773:7434b2271b0c Mon Dec 08 10:16:00 EST 2008 Nathan Binkert <nate@binkert.org> output: Change default output directory and files and update tests.
diff 5523:6279e78a2df2 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> sockets: Add a function to disable all listening sockets.
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb. Expose a function to disable those ports, and have the
regression scripts disable them. There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
H A Dconfig.pydiff 5471:576aa675d4e5 Sun Jun 15 00:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> Add .m5 configuration directory
H A D__init__.pydiff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5.

This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack. This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name. Additionally, a new Importer
was needed to allow python to get at the embedded python code.

Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things. Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.

The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
/gem5/src/cpu/simple/
H A Dbase.ccdiff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5665:433182bf55c1 Sun Oct 12 19:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5496:6899b894166f Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
diff 5348:7847a4bf9641 Thu Feb 14 16:14:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
/gem5/src/cpu/
H A Dbase_dyn_inst.hhdiff 5737:f43dbc09fad3 Mon Nov 10 14:51:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> O3CPU: Make the instcount debugging stuff per-cpu.
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
/gem5/configs/example/
H A Dse.pydiff 5514:9a903bf83a33 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> process: separate stderr from stdout
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout. The
new default maintains stdout and stderr going to the host. Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
diff 5457:08bd3709d482 Fri Jun 13 01:09:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Scripts: Check for the appropriate build type as soon as possible.
diff 5369:9358355117b0 Thu Feb 28 20:39:00 EST 2008 Ali Saidi <saidi@eecs.umich.edu> Configs: Fix some bugs we introduced in the simpoints code
/gem5/configs/common/
H A DOptions.pydiff 5361:e379019a1abd Wed Feb 27 00:35:00 EST 2008 Rick Strong <rstrong@cs.ucsd.edu> Configs: Make using Simpoints easier with some config files that support them easily
diff 5353:487d6f3291d7 Fri Feb 22 17:48:00 EST 2008 Vilas Sridharan <vilas.sridharan@gmail.com> add instruction count fast forwaing and max instruction options
/gem5/tests/configs/
H A Dtsunami-simple-timing-dual.pydiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
/gem5/src/arch/sparc/isa/formats/mem/
H A Dutil.isadiff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
/gem5/src/arch/x86/
H A Dtypes.hhdiff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code.
/gem5/src/arch/mips/isa/formats/
H A Dmem.isadiff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
/gem5/src/arch/
H A DSConscriptdiff 5664:3b3756efad89 Sun Oct 12 18:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
/gem5/src/arch/riscv/isa/
H A Ddecoder.isadiff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which include single- and double-precision floating point
instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
and patch 2 implemented the integer multiply extension, RV64M.

Patch 4 will implement the atomic memory instructions, RV64A, and patch
5 will add support for timing, minor, and detailed CPU models that is
missing from the first four patches.

[Fixed exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/mem/cache/tags/
H A Dbase.hh5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.

Completed in 344 milliseconds

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