12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 305268Sksewell@umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A /// Memory request flags. See mem_req_base.hh. 455736Snate@binkert.org Request::Flags memAccessFlags; 462239SN/A 472124SN/A /// Displacement for EA calculation (signed). 482124SN/A int32_t disp; 492124SN/A 502124SN/A /// Constructor 516207Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 532742Sksewell@umich.edu disp(sext<16>(OFFSET)) 542022SN/A { 552124SN/A } 562022SN/A 5712616Sgabeblack@google.com std::string generateDisassembly( 5812616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 592124SN/A }; 602124SN/A 612742Sksewell@umich.edu /** 622742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 632742Sksewell@umich.edu * that don't interpret the disp field 642742Sksewell@umich.edu */ 652742Sksewell@umich.edu class MemoryNoDisp : public Memory 662742Sksewell@umich.edu { 672742Sksewell@umich.edu protected: 682742Sksewell@umich.edu /// Constructor 696207Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706207Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 712742Sksewell@umich.edu { 722742Sksewell@umich.edu } 732742Sksewell@umich.edu 7412616Sgabeblack@google.com std::string generateDisassembly( 7512616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 762742Sksewell@umich.edu }; 772022SN/A}}; 782022SN/A 792124SN/A 802022SN/Aoutput decoder {{ 812124SN/A std::string 822124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832124SN/A { 842742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 862124SN/A } 872124SN/A 882742Sksewell@umich.edu std::string 892742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902742Sksewell@umich.edu { 912742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 932742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 942742Sksewell@umich.edu RS, RT); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 999554Sandreas.hansson@arm.comoutput header {{ 10012234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet); 1019554Sandreas.hansson@arm.com 1029554Sandreas.hansson@arm.com}}; 1039554Sandreas.hansson@arm.com 1044661Sksewell@umich.eduoutput exec {{ 1054661Sksewell@umich.edu /** return data in cases where there the size of data is only 1064661Sksewell@umich.edu known in the packet 1074661Sksewell@umich.edu */ 10812234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet) { 1094661Sksewell@umich.edu switch (packet->getSize()) 1104661Sksewell@umich.edu { 1115222Sksewell@umich.edu case 1: 11213233Sgabeblack@google.com return packet->getLE<uint8_t>(); 1134661Sksewell@umich.edu 1145222Sksewell@umich.edu case 2: 11513233Sgabeblack@google.com return packet->getLE<uint16_t>(); 1164661Sksewell@umich.edu 1175222Sksewell@umich.edu case 4: 11813233Sgabeblack@google.com return packet->getLE<uint32_t>(); 1194661Sksewell@umich.edu 1205222Sksewell@umich.edu case 8: 12113233Sgabeblack@google.com return packet->getLE<uint64_t>(); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu default: 12413449Sgabeblack@google.com panic("bad store data size = %d", packet->getSize()); 1254661Sksewell@umich.edu return 0; 1264661Sksewell@umich.edu } 1274661Sksewell@umich.edu } 1284661Sksewell@umich.edu 1294661Sksewell@umich.edu 1302022SN/A}}; 1312022SN/A 1322124SN/Adef template LoadStoreDeclare {{ 1332124SN/A /** 1342124SN/A * Static instruction class for "%(mnemonic)s". 1352124SN/A */ 1362124SN/A class %(class_name)s : public %(base_class)s 1372124SN/A { 1382124SN/A public: 1392124SN/A 1402124SN/A /// Constructor. 1414661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1422124SN/A 14312616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 14412616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 14512616Sgabeblack@google.com Fault completeAcc(Packet *, ExecContext *, 14612616Sgabeblack@google.com Trace::InstRecord *) const override; 1472124SN/A }; 1482022SN/A}}; 1492022SN/A 1502124SN/A 1516207Sksewell@umich.edudef template LoadStoreConstructor {{ 15210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst) 1536207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1542124SN/A { 1553953Sstever@eecs.umich.edu %(constructor)s; 1562124SN/A } 1573953Sstever@eecs.umich.edu}}; 1582124SN/A 1592124SN/Adef template LoadExecute {{ 16012234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1612124SN/A Trace::InstRecord *traceData) const 1622124SN/A { 1632124SN/A Addr EA; 1642132SN/A Fault fault = NoFault; 1652124SN/A 1665222Sksewell@umich.edu if (this->isFloating()) { 1675222Sksewell@umich.edu %(fp_enable_check)s; 1685222Sksewell@umich.edu 1695222Sksewell@umich.edu if(fault != NoFault) 1705222Sksewell@umich.edu return fault; 1715222Sksewell@umich.edu } 1725222Sksewell@umich.edu 1732124SN/A %(op_decl)s; 1742124SN/A %(op_rd)s; 1752124SN/A %(ea_code)s; 1762124SN/A 1772124SN/A if (fault == NoFault) { 1788442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1792124SN/A %(memacc_code)s; 1802124SN/A } 1812124SN/A 1822124SN/A if (fault == NoFault) { 1832124SN/A %(op_wb)s; 1842124SN/A } 1852124SN/A 1862124SN/A return fault; 1872124SN/A } 1882124SN/A}}; 1892124SN/A 1902124SN/A 1912124SN/Adef template LoadInitiateAcc {{ 19212234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1932124SN/A Trace::InstRecord *traceData) const 1942124SN/A { 1952239SN/A Addr EA; 1962132SN/A Fault fault = NoFault; 1972239SN/A 1985222Sksewell@umich.edu if (this->isFloating()) { 1995222Sksewell@umich.edu %(fp_enable_check)s; 2005222Sksewell@umich.edu 2015222Sksewell@umich.edu if(fault != NoFault) 2025222Sksewell@umich.edu return fault; 2035222Sksewell@umich.edu } 2045222Sksewell@umich.edu 2052239SN/A %(op_src_decl)s; 2062239SN/A %(op_rd)s; 2072239SN/A %(ea_code)s; 2082239SN/A 2092239SN/A if (fault == NoFault) { 21011303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 2112239SN/A } 2122239SN/A 2132124SN/A return fault; 2142124SN/A } 2152124SN/A}}; 2162124SN/A 2172124SN/Adef template LoadCompleteAcc {{ 21812234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 2192124SN/A Trace::InstRecord *traceData) const 2202124SN/A { 2212132SN/A Fault fault = NoFault; 2222239SN/A 2235222Sksewell@umich.edu if (this->isFloating()) { 2245222Sksewell@umich.edu %(fp_enable_check)s; 2255222Sksewell@umich.edu 2265222Sksewell@umich.edu if(fault != NoFault) 2275222Sksewell@umich.edu return fault; 2285222Sksewell@umich.edu } 2295222Sksewell@umich.edu 2302506SN/A %(op_decl)s; 2314661Sksewell@umich.edu %(op_rd)s; 2322239SN/A 2338442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2342239SN/A 2352239SN/A if (fault == NoFault) { 2362239SN/A %(memacc_code)s; 2372239SN/A } 2382239SN/A 2392239SN/A if (fault == NoFault) { 2402239SN/A %(op_wb)s; 2412239SN/A } 2422239SN/A 2432124SN/A return fault; 2442124SN/A } 2452124SN/A}}; 2462124SN/A 2472124SN/Adef template StoreExecute {{ 24812234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2492124SN/A Trace::InstRecord *traceData) const 2502124SN/A { 2512124SN/A Addr EA; 2522132SN/A Fault fault = NoFault; 2534056Sstever@eecs.umich.edu 2544056Sstever@eecs.umich.edu %(fp_enable_check)s; 2554056Sstever@eecs.umich.edu %(op_decl)s; 2564056Sstever@eecs.umich.edu %(op_rd)s; 2574056Sstever@eecs.umich.edu %(ea_code)s; 2584056Sstever@eecs.umich.edu 2594056Sstever@eecs.umich.edu if (fault == NoFault) { 2604056Sstever@eecs.umich.edu %(memacc_code)s; 2614056Sstever@eecs.umich.edu } 2624056Sstever@eecs.umich.edu 2634056Sstever@eecs.umich.edu if (fault == NoFault) { 2648442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 2658442Sgblack@eecs.umich.edu NULL); 2664056Sstever@eecs.umich.edu } 2674056Sstever@eecs.umich.edu 2684056Sstever@eecs.umich.edu if (fault == NoFault) { 2694056Sstever@eecs.umich.edu %(postacc_code)s; 2704056Sstever@eecs.umich.edu } 2714056Sstever@eecs.umich.edu 2724056Sstever@eecs.umich.edu if (fault == NoFault) { 2734056Sstever@eecs.umich.edu %(op_wb)s; 2744056Sstever@eecs.umich.edu } 2754056Sstever@eecs.umich.edu 2764056Sstever@eecs.umich.edu return fault; 2774056Sstever@eecs.umich.edu } 2784056Sstever@eecs.umich.edu}}; 2794056Sstever@eecs.umich.edu 2805222Sksewell@umich.edu 2815222Sksewell@umich.edudef template StoreFPExecute {{ 28212234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2835222Sksewell@umich.edu Trace::InstRecord *traceData) const 2845222Sksewell@umich.edu { 2855222Sksewell@umich.edu Addr EA; 2865222Sksewell@umich.edu Fault fault = NoFault; 2875222Sksewell@umich.edu 2885222Sksewell@umich.edu %(fp_enable_check)s; 2895222Sksewell@umich.edu if(fault != NoFault) 2905222Sksewell@umich.edu return fault; 2915222Sksewell@umich.edu %(op_decl)s; 2925222Sksewell@umich.edu %(op_rd)s; 2935222Sksewell@umich.edu %(ea_code)s; 2945222Sksewell@umich.edu 2955222Sksewell@umich.edu if (fault == NoFault) { 2965222Sksewell@umich.edu %(memacc_code)s; 2975222Sksewell@umich.edu } 2985222Sksewell@umich.edu 2995222Sksewell@umich.edu if (fault == NoFault) { 3008442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3018442Sgblack@eecs.umich.edu NULL); 3025222Sksewell@umich.edu } 3035222Sksewell@umich.edu 3045222Sksewell@umich.edu if (fault == NoFault) { 3055222Sksewell@umich.edu %(postacc_code)s; 3065222Sksewell@umich.edu } 3075222Sksewell@umich.edu 3085222Sksewell@umich.edu if (fault == NoFault) { 3095222Sksewell@umich.edu %(op_wb)s; 3105222Sksewell@umich.edu } 3115222Sksewell@umich.edu 3125222Sksewell@umich.edu return fault; 3135222Sksewell@umich.edu } 3145222Sksewell@umich.edu}}; 3155222Sksewell@umich.edu 3164056Sstever@eecs.umich.edudef template StoreCondExecute {{ 31712234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3184056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3194056Sstever@eecs.umich.edu { 3204056Sstever@eecs.umich.edu Addr EA; 3214056Sstever@eecs.umich.edu Fault fault = NoFault; 3222124SN/A uint64_t write_result = 0; 3232124SN/A 3242124SN/A %(fp_enable_check)s; 3252124SN/A %(op_decl)s; 3262124SN/A %(op_rd)s; 3272124SN/A %(ea_code)s; 3282124SN/A 3292124SN/A if (fault == NoFault) { 3302124SN/A %(memacc_code)s; 3312124SN/A } 3322124SN/A 3332124SN/A if (fault == NoFault) { 3348442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3358442Sgblack@eecs.umich.edu &write_result); 3362124SN/A } 3372124SN/A 3382124SN/A if (fault == NoFault) { 3392124SN/A %(postacc_code)s; 3402124SN/A } 3412124SN/A 3422124SN/A if (fault == NoFault) { 3432124SN/A %(op_wb)s; 3442124SN/A } 3452124SN/A 3462124SN/A return fault; 3472124SN/A } 3482124SN/A}}; 3492124SN/A 3502124SN/Adef template StoreInitiateAcc {{ 35112234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3522124SN/A Trace::InstRecord *traceData) const 3532124SN/A { 3542239SN/A Addr EA; 3552132SN/A Fault fault = NoFault; 3562239SN/A 3572239SN/A %(fp_enable_check)s; 3582506SN/A %(op_decl)s; 3592239SN/A %(op_rd)s; 3602239SN/A %(ea_code)s; 3612239SN/A 3622239SN/A if (fault == NoFault) { 3632239SN/A %(memacc_code)s; 3642239SN/A } 3652239SN/A 3662239SN/A if (fault == NoFault) { 3678442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3688442Sgblack@eecs.umich.edu NULL); 3692239SN/A } 3702239SN/A 3712124SN/A return fault; 3722124SN/A } 3732124SN/A}}; 3742124SN/A 3752124SN/A 3762124SN/Adef template StoreCompleteAcc {{ 3774661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 37812234Sgabeblack@google.com ExecContext *xc, 3792124SN/A Trace::InstRecord *traceData) const 3802124SN/A { 3817712Sgblack@eecs.umich.edu return NoFault; 3822935Sksewell@umich.edu } 3832935Sksewell@umich.edu}}; 3842935Sksewell@umich.edu 3852935Sksewell@umich.edudef template StoreCondCompleteAcc {{ 3864661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 38712234Sgabeblack@google.com ExecContext *xc, 3882935Sksewell@umich.edu Trace::InstRecord *traceData) const 3892935Sksewell@umich.edu { 3902935Sksewell@umich.edu Fault fault = NoFault; 3912935Sksewell@umich.edu 3922935Sksewell@umich.edu %(fp_enable_check)s; 3932935Sksewell@umich.edu %(op_dest_decl)s; 3942935Sksewell@umich.edu 3954055Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3962239SN/A 3972239SN/A if (fault == NoFault) { 3982239SN/A %(postacc_code)s; 3992239SN/A } 4002239SN/A 4012239SN/A if (fault == NoFault) { 4022239SN/A %(op_wb)s; 4032239SN/A } 4042239SN/A 4052124SN/A return fault; 4062124SN/A } 4072124SN/A}}; 4082124SN/A 4092686Sksewell@umich.edudef template MiscExecute {{ 41012234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 4112686Sksewell@umich.edu Trace::InstRecord *traceData) const 4122686Sksewell@umich.edu { 4137725SAli.Saidi@ARM.com Addr EA M5_VAR_USED = 0; 4142686Sksewell@umich.edu Fault fault = NoFault; 4152686Sksewell@umich.edu 4162686Sksewell@umich.edu %(fp_enable_check)s; 4172686Sksewell@umich.edu %(op_decl)s; 4182686Sksewell@umich.edu %(op_rd)s; 4192686Sksewell@umich.edu %(ea_code)s; 4202686Sksewell@umich.edu 4212686Sksewell@umich.edu if (fault == NoFault) { 4222686Sksewell@umich.edu %(memacc_code)s; 4232686Sksewell@umich.edu } 4242686Sksewell@umich.edu 4252686Sksewell@umich.edu return NoFault; 4262686Sksewell@umich.edu } 4272686Sksewell@umich.edu}}; 4282686Sksewell@umich.edu 4292686Sksewell@umich.edudef template MiscInitiateAcc {{ 43012234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4312686Sksewell@umich.edu Trace::InstRecord *traceData) const 4322686Sksewell@umich.edu { 4332686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4342686Sksewell@umich.edu return NoFault; 4352686Sksewell@umich.edu } 4362686Sksewell@umich.edu}}; 4372686Sksewell@umich.edu 4382686Sksewell@umich.edu 4392686Sksewell@umich.edudef template MiscCompleteAcc {{ 44012234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 4412686Sksewell@umich.edu Trace::InstRecord *traceData) const 4422686Sksewell@umich.edu { 4432686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4442686Sksewell@umich.edu 4452686Sksewell@umich.edu return NoFault; 4462686Sksewell@umich.edu } 4472686Sksewell@umich.edu}}; 4482686Sksewell@umich.edu 4492124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4502124SN/A mem_flags = [], inst_flags = []) {{ 4512124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4522124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4532750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4542124SN/A exec_template_base = 'Load') 4552124SN/A}}; 4562124SN/A 4575222Sksewell@umich.edu 4582124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4592124SN/A mem_flags = [], inst_flags = []) {{ 4602124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4612124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4622124SN/A exec_template_base = 'Store') 4632124SN/A}}; 4642124SN/A 4652686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4662573SN/A mem_flags = [], inst_flags = []) {{ 4675222Sksewell@umich.edu inst_flags += ['IsIndexed'] 4682573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4692573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4702750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4712573SN/A exec_template_base = 'Load') 4722573SN/A}}; 4732573SN/A 4742686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4752573SN/A mem_flags = [], inst_flags = []) {{ 4765222Sksewell@umich.edu inst_flags += ['IsIndexed'] 4772573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4782573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4792573SN/A exec_template_base = 'Store') 4802573SN/A}}; 4812573SN/A 4825222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4835222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4845222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 4855222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4865222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4875222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4885222Sksewell@umich.edu exec_template_base = 'Load') 4895222Sksewell@umich.edu}}; 4905222Sksewell@umich.edu 4915222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 4925222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 4935222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 4945222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4955222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4965222Sksewell@umich.edu exec_template_base = 'Store') 4975222Sksewell@umich.edu}}; 4985222Sksewell@umich.edu 4995222Sksewell@umich.edu 5002686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5012686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5028564Sgblack@eecs.umich.edu decl_code = ''' 5038588Sgblack@eecs.umich.edu uint32_t mem_word = Mem_uw; 5048564Sgblack@eecs.umich.edu uint32_t unalign_addr = Rs + disp; 5058564Sgblack@eecs.umich.edu uint32_t byte_offset = unalign_addr & 3; 5068564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5078564Sgblack@eecs.umich.edu byte_offset ^= 3; 5088564Sgblack@eecs.umich.edu ''' 5092573SN/A 5102686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5112686Sksewell@umich.edu 5122686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5132686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5142750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5152686Sksewell@umich.edu exec_template_base = 'Load') 5162686Sksewell@umich.edu}}; 5172686Sksewell@umich.edu 5182686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5192686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5208442Sgblack@eecs.umich.edu decl_code = ''' 5218442Sgblack@eecs.umich.edu uint32_t mem_word = 0; 5228442Sgblack@eecs.umich.edu uint32_t unaligned_addr = Rs + disp; 5238442Sgblack@eecs.umich.edu uint32_t byte_offset = unaligned_addr & 3; 5248564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5258442Sgblack@eecs.umich.edu byte_offset ^= 3; 5268442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 5278442Sgblack@eecs.umich.edu ''' 5282686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5292686Sksewell@umich.edu 5302686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5312686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5322686Sksewell@umich.edu exec_template_base = 'Store') 5332686Sksewell@umich.edu}}; 5342686Sksewell@umich.edu 5352686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5362686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5376739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5387725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5392686Sksewell@umich.edu 5402686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5412686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5427725SAli.Saidi@ARM.com 'warn_once("Prefetching not implemented for MIPS\\n");', 5432686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5442686Sksewell@umich.edu 5452686Sksewell@umich.edu}}; 5462686Sksewell@umich.edu 5472686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5482686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5492495SN/A mem_flags = [], inst_flags = []) {{ 5502495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5512495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5522935Sksewell@umich.edu postacc_code, exec_template_base = 'StoreCond') 5532495SN/A}}; 554