1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_TYPES_HH__
41#define __ARCH_X86_TYPES_HH__
42
43#include <iostream>
44
45#include "arch/generic/types.hh"
46#include "base/bitunion.hh"
47#include "base/cprintf.hh"
48#include "base/types.hh"
49#include "sim/serialize.hh"
50
51namespace X86ISA
52{
53    //This really determines how many bytes are passed to the decoder.
54    typedef uint64_t MachInst;
55
56    enum Prefixes {
57        NoOverride,
58        ESOverride,
59        CSOverride,
60        SSOverride,
61        DSOverride,
62        FSOverride,
63        GSOverride,
64        RexPrefix,
65        OperandSizeOverride,
66        AddressSizeOverride,
67        Lock,
68        Rep,
69        Repne,
70        Vex2Prefix,
71        Vex3Prefix,
72        XopPrefix,
73    };
74
75    BitUnion8(LegacyPrefixVector)
76        Bitfield<7, 4> decodeVal;
77        Bitfield<7> repne;
78        Bitfield<6> rep;
79        Bitfield<5> lock;
80        Bitfield<4> op;
81        Bitfield<3> addr;
82        //There can be only one segment override, so they share the
83        //first 3 bits in the legacyPrefixes bitfield.
84        Bitfield<2,0> seg;
85    EndBitUnion(LegacyPrefixVector)
86
87    BitUnion8(ModRM)
88        Bitfield<7,6> mod;
89        Bitfield<5,3> reg;
90        Bitfield<2,0> rm;
91    EndBitUnion(ModRM)
92
93    BitUnion8(Sib)
94        Bitfield<7,6> scale;
95        Bitfield<5,3> index;
96        Bitfield<2,0> base;
97    EndBitUnion(Sib)
98
99    BitUnion8(Rex)
100        //This bit doesn't mean anything according to the ISA, but in
101        //this implementation, it being set means an REX prefix was present.
102        Bitfield<6> present;
103        Bitfield<3> w;
104        Bitfield<2> r;
105        Bitfield<1> x;
106        Bitfield<0> b;
107    EndBitUnion(Rex)
108
109    BitUnion8(Vex2Of3)
110        // Inverted bits from the REX prefix.
111        Bitfield<7> r;
112        Bitfield<6> x;
113        Bitfield<5> b;
114        // Selector for what would be two or three byte opcode types.
115        Bitfield<4, 0> m;
116    EndBitUnion(Vex2Of3)
117
118    BitUnion8(Vex3Of3)
119        // Bit from the REX prefix.
120        Bitfield<7> w;
121        // Inverted extra register index.
122        Bitfield<6, 3>  v;
123        // Vector length specifier.
124        Bitfield<2> l;
125        // Implied 66, F2, or F3 opcode prefix.
126        Bitfield<1, 0> p;
127    EndBitUnion(Vex3Of3)
128
129    BitUnion8(Vex2Of2)
130        // Inverted bit from the REX prefix.
131        Bitfield<7> r;
132        // Inverted extra register index.
133        Bitfield<6, 3>  v;
134        // Vector length specifier
135        Bitfield<2> l;
136        // Implied 66, F2, or F3 opcode prefix.
137        Bitfield<1, 0> p;
138    EndBitUnion(Vex2Of2)
139
140    BitUnion8(VexInfo)
141        // Extra register index.
142        Bitfield<6, 3> v;
143        // Vector length specifier.
144        Bitfield<2> l;
145        // Whether the VEX prefix was used.
146        Bitfield<0> present;
147    EndBitUnion(VexInfo)
148
149    enum OpcodeType {
150        BadOpcode,
151        OneByteOpcode,
152        TwoByteOpcode,
153        ThreeByte0F38Opcode,
154        ThreeByte0F3AOpcode,
155    };
156
157    static inline const char *
158    opcodeTypeToStr(OpcodeType type)
159    {
160        switch (type) {
161          case BadOpcode:
162            return "bad";
163          case OneByteOpcode:
164            return "one byte";
165          case TwoByteOpcode:
166            return "two byte";
167          case ThreeByte0F38Opcode:
168            return "three byte 0f38";
169          case ThreeByte0F3AOpcode:
170            return "three byte 0f3a";
171          default:
172            return "unrecognized!";
173        }
174    }
175
176    BitUnion8(Opcode)
177        Bitfield<7,3> top5;
178        Bitfield<2,0> bottom3;
179    EndBitUnion(Opcode)
180
181    BitUnion8(OperatingMode)
182        Bitfield<3> mode;
183        Bitfield<2,0> submode;
184    EndBitUnion(OperatingMode)
185
186    enum X86Mode {
187        LongMode,
188        LegacyMode
189    };
190
191    enum X86SubMode {
192        SixtyFourBitMode,
193        CompatabilityMode,
194        ProtectedMode,
195        Virtual8086Mode,
196        RealMode
197    };
198
199    //The intermediate structure used by the x86 decoder.
200    struct ExtMachInst
201    {
202        void reset() {
203            memset(static_cast<void *>(this), 0, sizeof(*this));
204        }
205
206        //Prefixes
207        LegacyPrefixVector legacy;
208        Rex rex;
209        VexInfo vex;
210
211        //This holds all of the bytes of the opcode
212        struct
213        {
214            OpcodeType type;
215            //The main opcode byte. The highest addressed byte in the opcode.
216            Opcode op;
217        } opcode;
218        //Modifier bytes
219        ModRM modRM;
220        Sib sib;
221        //Immediate fields
222        uint64_t immediate;
223        uint64_t displacement;
224
225        //The effective operand size.
226        uint8_t opSize;
227        //The effective address size.
228        uint8_t addrSize;
229        //The effective stack size.
230        uint8_t stackSize;
231        //The size of the displacement
232        uint8_t dispSize;
233
234        //Mode information
235        OperatingMode mode;
236    };
237
238    inline static std::ostream &
239        operator << (std::ostream & os, const ExtMachInst & emi)
240    {
241        ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
242                     "vex/xop = %#x,\n\t"
243                     "op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
244                     "modRM = %#x,\n\tsib = %#x,\n\t"
245                     "immediate = %#x,\n\tdisplacement = %#x\n\t"
246                     "dispSize = %d}\n",
247                     (uint8_t)emi.legacy, (uint8_t)emi.rex,
248                     (uint8_t)emi.vex,
249                     opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
250                     (uint8_t)emi.modRM, (uint8_t)emi.sib,
251                     emi.immediate, emi.displacement, emi.dispSize);
252        return os;
253    }
254
255    inline static bool
256        operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
257    {
258        if (emi1.legacy != emi2.legacy)
259            return false;
260        if (emi1.rex != emi2.rex)
261            return false;
262        if (emi1.vex != emi2.vex)
263            return false;
264        if (emi1.opcode.type != emi2.opcode.type)
265            return false;
266        if (emi1.opcode.op != emi2.opcode.op)
267            return false;
268        if (emi1.modRM != emi2.modRM)
269            return false;
270        if (emi1.sib != emi2.sib)
271            return false;
272        if (emi1.immediate != emi2.immediate)
273            return false;
274        if (emi1.displacement != emi2.displacement)
275            return false;
276        if (emi1.mode != emi2.mode)
277            return false;
278        if (emi1.opSize != emi2.opSize)
279            return false;
280        if (emi1.addrSize != emi2.addrSize)
281            return false;
282        if (emi1.stackSize != emi2.stackSize)
283            return false;
284        if (emi1.dispSize != emi2.dispSize)
285            return false;
286        return true;
287    }
288
289    class PCState : public GenericISA::UPCState<MachInst>
290    {
291      protected:
292        typedef GenericISA::UPCState<MachInst> Base;
293
294        uint8_t _size;
295
296      public:
297        void
298        set(Addr val)
299        {
300            Base::set(val);
301            _size = 0;
302        }
303
304        PCState() {}
305        PCState(Addr val) { set(val); }
306
307        void
308        setNPC(Addr val)
309        {
310            Base::setNPC(val);
311            _size = 0;
312        }
313
314        uint8_t size() const { return _size; }
315        void size(uint8_t newSize) { _size = newSize; }
316
317        bool
318        branching() const
319        {
320            return (this->npc() != this->pc() + size()) ||
321                   (this->nupc() != this->upc() + 1);
322        }
323
324        void
325        advance()
326        {
327            Base::advance();
328            _size = 0;
329        }
330
331        void
332        uEnd()
333        {
334            Base::uEnd();
335            _size = 0;
336        }
337
338        void
339        serialize(CheckpointOut &cp) const
340        {
341            Base::serialize(cp);
342            SERIALIZE_SCALAR(_size);
343        }
344
345        void
346        unserialize(CheckpointIn &cp)
347        {
348            Base::unserialize(cp);
349            UNSERIALIZE_SCALAR(_size);
350        }
351    };
352
353}
354
355namespace std {
356    template<>
357    struct hash<X86ISA::ExtMachInst> {
358        size_t operator()(const X86ISA::ExtMachInst &emi) const {
359            return (((uint64_t)emi.legacy << 48) |
360                    ((uint64_t)emi.rex << 40) |
361                    ((uint64_t)emi.vex << 32) |
362                    ((uint64_t)emi.modRM << 24) |
363                    ((uint64_t)emi.sib << 16) |
364                    ((uint64_t)emi.opcode.type << 8) |
365                    ((uint64_t)emi.opcode.op)) ^
366                    emi.immediate ^ emi.displacement ^
367                    emi.mode ^
368                    emi.opSize ^ emi.addrSize ^
369                    emi.stackSize ^ emi.dispSize;
370        };
371    };
372}
373
374// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
375// and UNSERIALIZE_SCALAR.
376template <>
377void
378paramOut(CheckpointOut &cp, const std::string &name,
379         const X86ISA::ExtMachInst &machInst);
380template <>
381void
382paramIn(CheckpointIn &cp, const std::string &name,
383        X86ISA::ExtMachInst &machInst);
384
385#endif // __ARCH_X86_TYPES_HH__
386