11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421060SN/A 432292SN/A#ifndef __CPU_O3_DECODE_HH__ 442292SN/A#define __CPU_O3_DECODE_HH__ 451060SN/A 461060SN/A#include <queue> 471060SN/A 481461SN/A#include "base/statistics.hh" 497813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 501060SN/A 518737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 525529Snate@binkert.org 532292SN/A/** 542329SN/A * DefaultDecode class handles both single threaded and SMT 552329SN/A * decode. Its width is specified by the parameters; each cycles it 562329SN/A * tries to decode that many instructions. Because instructions are 572329SN/A * actually decoded when the StaticInst is created, this stage does 582329SN/A * not do much other than check any PC-relative branches. 592292SN/A */ 601060SN/Atemplate<class Impl> 612292SN/Aclass DefaultDecode 621060SN/A{ 631060SN/A private: 641060SN/A // Typedefs from the Impl. 652733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 661061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 671061SN/A typedef typename Impl::CPUPol CPUPol; 681060SN/A 691061SN/A // Typedefs from the CPU policy. 701061SN/A typedef typename CPUPol::FetchStruct FetchStruct; 711061SN/A typedef typename CPUPol::DecodeStruct DecodeStruct; 721061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 731060SN/A 741060SN/A public: 752292SN/A /** Overall decode stage status. Used to determine if the CPU can 762292SN/A * deschedule itself due to a lack of activity. 772292SN/A */ 782292SN/A enum DecodeStatus { 792292SN/A Active, 802292SN/A Inactive 812292SN/A }; 822292SN/A 832292SN/A /** Individual thread status. */ 842292SN/A enum ThreadStatus { 851060SN/A Running, 861060SN/A Idle, 872292SN/A StartSquash, 881060SN/A Squashing, 891060SN/A Blocked, 901060SN/A Unblocking 911060SN/A }; 921060SN/A 931060SN/A private: 942292SN/A /** Decode status. */ 952292SN/A DecodeStatus _status; 962292SN/A 972292SN/A /** Per-thread status. */ 982292SN/A ThreadStatus decodeStatus[Impl::MaxThreads]; 991060SN/A 1001060SN/A public: 1012292SN/A /** DefaultDecode constructor. */ 1025529Snate@binkert.org DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params); 1031060SN/A 1049444SAndreas.Sandberg@ARM.com void startupStage(); 10513641Sqtt2@cornell.edu 10613641Sqtt2@cornell.edu /** Clear all thread-specific states */ 10713641Sqtt2@cornell.edu void clearStates(ThreadID tid); 10813641Sqtt2@cornell.edu 1099444SAndreas.Sandberg@ARM.com void resetStage(); 1109444SAndreas.Sandberg@ARM.com 1112292SN/A /** Returns the name of decode. */ 1122292SN/A std::string name() const; 1132292SN/A 1142292SN/A /** Registers statistics. */ 1151062SN/A void regStats(); 1161062SN/A 1172292SN/A /** Sets the main backwards communication time buffer pointer. */ 1181060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1191060SN/A 1202292SN/A /** Sets pointer to time buffer used to communicate to the next stage. */ 1211060SN/A void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr); 1221060SN/A 1232292SN/A /** Sets pointer to time buffer coming from fetch. */ 1241060SN/A void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 1251060SN/A 1262292SN/A /** Sets pointer to list of active threads. */ 1276221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1282292SN/A 1299444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1309444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1312843Sktlim@umich.edu 1329444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 13310328Smitch.hayenga@arm.com bool isDrained() const; 1342307SN/A 1352348SN/A /** Takes over from another CPU's thread. */ 1369444SAndreas.Sandberg@ARM.com void takeOverFrom() { resetStage(); } 1372348SN/A 1382292SN/A /** Ticks decode, processing all input signals and decoding as many 1392292SN/A * instructions as possible. 1402292SN/A */ 1411060SN/A void tick(); 1421060SN/A 1432292SN/A /** Determines what to do based on decode's current status. 1442292SN/A * @param status_change decode() sets this variable if there was a status 1452292SN/A * change (ie switching from from blocking to unblocking). 1462292SN/A * @param tid Thread id to decode instructions from. 1472292SN/A */ 1486221Snate@binkert.org void decode(bool &status_change, ThreadID tid); 1492292SN/A 1502292SN/A /** Processes instructions from fetch and passes them on to rename. 1512292SN/A * Decoding of instructions actually happens when they are created in 1522292SN/A * fetch, so this function mostly checks if PC-relative branches are 1532292SN/A * correct. 1542292SN/A */ 1556221Snate@binkert.org void decodeInsts(ThreadID tid); 1561060SN/A 1571060SN/A private: 1582292SN/A /** Inserts a thread's instructions into the skid buffer, to be decoded 1592292SN/A * once decode unblocks. 1602292SN/A */ 1616221Snate@binkert.org void skidInsert(ThreadID tid); 1622292SN/A 1632292SN/A /** Returns if all of the skid buffers are empty. */ 1642292SN/A bool skidsEmpty(); 1652292SN/A 1662292SN/A /** Updates overall decode status based on all of the threads' statuses. */ 1672292SN/A void updateStatus(); 1682292SN/A 1692292SN/A /** Separates instructions from fetch into individual lists of instructions 1702292SN/A * sorted by thread. 1712292SN/A */ 1722292SN/A void sortInsts(); 1732292SN/A 1742292SN/A /** Reads all stall signals from the backwards communication timebuffer. */ 1756221Snate@binkert.org void readStallSignals(ThreadID tid); 1762292SN/A 1772292SN/A /** Checks all input signals and updates decode's status appropriately. */ 1786221Snate@binkert.org bool checkSignalsAndUpdate(ThreadID tid); 1792292SN/A 1802292SN/A /** Checks all stall signals, and returns if any are true. */ 1816221Snate@binkert.org bool checkStall(ThreadID tid) const; 1822292SN/A 1832292SN/A /** Returns if there any instructions from fetch on this cycle. */ 1841681SN/A inline bool fetchInstsValid(); 1851681SN/A 1862292SN/A /** Switches decode to blocking, and signals back that decode has 1872292SN/A * become blocked. 1882292SN/A * @return Returns true if there is a status change. 1892292SN/A */ 1906221Snate@binkert.org bool block(ThreadID tid); 1911060SN/A 1922292SN/A /** Switches decode to unblocking if the skid buffer is empty, and 1932292SN/A * signals back that decode has unblocked. 1942292SN/A * @return Returns true if there is a status change. 1952292SN/A */ 1966221Snate@binkert.org bool unblock(ThreadID tid); 1971060SN/A 1982292SN/A /** Squashes if there is a PC-relative branch that was predicted 1992292SN/A * incorrectly. Sends squash information back to fetch. 2002292SN/A */ 20113429Srekai.gonzalezalberquilla@arm.com void squash(const DynInstPtr &inst, ThreadID tid); 2021060SN/A 2031684SN/A public: 2042292SN/A /** Squashes due to commit signalling a squash. Changes status to 2052292SN/A * squashing and clears block/unblock signals as needed. 2062292SN/A */ 2076221Snate@binkert.org unsigned squash(ThreadID tid); 2081681SN/A 2091684SN/A private: 2101060SN/A // Interfaces to objects outside of decode. 2111060SN/A /** CPU interface. */ 2122733Sktlim@umich.edu O3CPU *cpu; 2131060SN/A 2141060SN/A /** Time buffer interface. */ 2151060SN/A TimeBuffer<TimeStruct> *timeBuffer; 2161060SN/A 2171060SN/A /** Wire to get rename's output from backwards time buffer. */ 2181060SN/A typename TimeBuffer<TimeStruct>::wire fromRename; 2191060SN/A 2201060SN/A /** Wire to get iew's information from backwards time buffer. */ 2211060SN/A typename TimeBuffer<TimeStruct>::wire fromIEW; 2221060SN/A 2231060SN/A /** Wire to get commit's information from backwards time buffer. */ 2241060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 2251060SN/A 2261060SN/A /** Wire to write information heading to previous stages. */ 2271060SN/A // Might not be the best name as not only fetch will read it. 2281060SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 2291060SN/A 2301060SN/A /** Decode instruction queue. */ 2311060SN/A TimeBuffer<DecodeStruct> *decodeQueue; 2321060SN/A 2331060SN/A /** Wire used to write any information heading to rename. */ 2341060SN/A typename TimeBuffer<DecodeStruct>::wire toRename; 2351060SN/A 2361060SN/A /** Fetch instruction queue interface. */ 2371060SN/A TimeBuffer<FetchStruct> *fetchQueue; 2381060SN/A 2391060SN/A /** Wire to get fetch's output from fetch queue. */ 2401060SN/A typename TimeBuffer<FetchStruct>::wire fromFetch; 2411060SN/A 2422292SN/A /** Queue of all instructions coming from fetch this cycle. */ 2432292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 2442292SN/A 2451060SN/A /** Skid buffer between fetch and decode. */ 2462292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 2471060SN/A 2482292SN/A /** Variable that tracks if decode has written to the time buffer this 2492292SN/A * cycle. Used to tell CPU if there is activity this cycle. 2502292SN/A */ 2512292SN/A bool wroteToTimeBuffer; 2522292SN/A 2532292SN/A /** Source of possible stalls. */ 2542292SN/A struct Stalls { 2552292SN/A bool rename; 2562292SN/A }; 2572292SN/A 2582292SN/A /** Tracks which stages are telling decode to stall. */ 2592292SN/A Stalls stalls[Impl::MaxThreads]; 2602292SN/A 2619184Sandreas.hansson@arm.com /** Rename to decode delay. */ 2629184Sandreas.hansson@arm.com Cycles renameToDecodeDelay; 2631060SN/A 2649184Sandreas.hansson@arm.com /** IEW to decode delay. */ 2659184Sandreas.hansson@arm.com Cycles iewToDecodeDelay; 2661060SN/A 2679184Sandreas.hansson@arm.com /** Commit to decode delay. */ 2689184Sandreas.hansson@arm.com Cycles commitToDecodeDelay; 2691060SN/A 2709184Sandreas.hansson@arm.com /** Fetch to decode delay. */ 2719184Sandreas.hansson@arm.com Cycles fetchToDecodeDelay; 2721060SN/A 2731060SN/A /** The width of decode, in instructions. */ 2741060SN/A unsigned decodeWidth; 2751061SN/A 2762292SN/A /** Index of instructions being sent to rename. */ 2772292SN/A unsigned toRenameIndex; 2782292SN/A 2792292SN/A /** number of Active Threads*/ 2806221Snate@binkert.org ThreadID numThreads; 2812292SN/A 2822292SN/A /** List of active thread ids */ 2836221Snate@binkert.org std::list<ThreadID> *activeThreads; 2842292SN/A 2852292SN/A /** Maximum size of the skid buffer. */ 2862292SN/A unsigned skidBufferMax; 2872292SN/A 2882935Sksewell@umich.edu /** SeqNum of Squashing Branch Delay Instruction (used for MIPS)*/ 2892935Sksewell@umich.edu Addr bdelayDoneSeqNum[Impl::MaxThreads]; 2902935Sksewell@umich.edu 2912935Sksewell@umich.edu /** Instruction used for squashing branch (used for MIPS)*/ 2922935Sksewell@umich.edu DynInstPtr squashInst[Impl::MaxThreads]; 2932935Sksewell@umich.edu 2942935Sksewell@umich.edu /** Tells when their is a pending delay slot inst. to send 2952935Sksewell@umich.edu * to rename. If there is, then wait squash after the next 2962935Sksewell@umich.edu * instruction (used for MIPS). 2972935Sksewell@umich.edu */ 2982935Sksewell@umich.edu bool squashAfterDelaySlot[Impl::MaxThreads]; 2992935Sksewell@umich.edu 3002935Sksewell@umich.edu 3012292SN/A /** Stat for total number of idle cycles. */ 3025999Snate@binkert.org Stats::Scalar decodeIdleCycles; 3032292SN/A /** Stat for total number of blocked cycles. */ 3045999Snate@binkert.org Stats::Scalar decodeBlockedCycles; 3052292SN/A /** Stat for total number of normal running cycles. */ 3065999Snate@binkert.org Stats::Scalar decodeRunCycles; 3072292SN/A /** Stat for total number of unblocking cycles. */ 3085999Snate@binkert.org Stats::Scalar decodeUnblockCycles; 3092292SN/A /** Stat for total number of squashing cycles. */ 3105999Snate@binkert.org Stats::Scalar decodeSquashCycles; 3112307SN/A /** Stat for number of times a branch is resolved at decode. */ 3125999Snate@binkert.org Stats::Scalar decodeBranchResolved; 3132292SN/A /** Stat for number of times a branch mispredict is detected. */ 3145999Snate@binkert.org Stats::Scalar decodeBranchMispred; 3152292SN/A /** Stat for number of times decode detected a non-control instruction 3162292SN/A * incorrectly predicted as a branch. 3171061SN/A */ 3185999Snate@binkert.org Stats::Scalar decodeControlMispred; 3192292SN/A /** Stat for total number of decoded instructions. */ 3205999Snate@binkert.org Stats::Scalar decodeDecodedInsts; 3212292SN/A /** Stat for total number of squashed instructions. */ 3225999Snate@binkert.org Stats::Scalar decodeSquashedInsts; 3231060SN/A}; 3241060SN/A 3252292SN/A#endif // __CPU_O3_DECODE_HH__ 326