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13931:31e62b71cca6 |
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04-Apr-2019 |
Avishai Tvila <avishai.tvila@gmail.com> |
arch-riscv,isa: Fix for compressed jump (c_j) imm
c_j(al) has a special format, called CJ. The jump offset format is instbits[12:2] --> offset[11|4|9:8|10|6|7|3:1|5] Currently in decoder.isa, c_j format is JOp, the imm and branchTarget are incorrect In the execute section (decoder.isa:228), the imm fields is ignored and the offset is calculated correctlly. As a result, we get decoder flush for each c_j instance I've added CJOp format in compressed.isa, and use it in execute section. In addition, c_j is mappped to jal zero, cj_imm, and actually is neither indirect control nor a function call I fixed the flags accordently. I'll fix all IsRet, IsCall and IsIndirectControl flags for rest of (c_)jal(r) in my next commit. I ran coremark -O0 before my fix and I got 37.7% branch miss-rate, after the fix the branch miss-rate is <13%
Change-Id: I608d5894a78a1ebefe36f21e21aaea68b42bccfc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17808 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
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13653:079472978bca |
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12-Feb-2018 |
Tuan Ta <qtt2@cornell.edu> |
riscv: fix AMO, LR and SC instructions
(1) Atomic Memory Operation (AMO)
This patch changes how RISC-V AMO instructions are implemented. For each AMO, instead of issuing a locking load and an unlocking store request to downstream memory system, this patch issues a single memory request that contains a corresponding AtomicOpFunctor to the memory system. Once the memory system receives the request, the atomic operation is executed in one single step.
This patch also changes how AMO instructions handle acquire and release flags in AMOs (e.g., amoadd.aq and amoadd.rl). If an AMO is associated with an acquire flag, a memory fence is inserted after the AMO completes as a micro-op. If an AMO is associated with a release flag, another memory fence is inserted before the AMO executes. If both flags are specified, the AMO is broken down into a sequence of 3 micro-ops: mem fence -> atomic RMW -> mem fence. This change makes this AMO implementation comply to the release consistency model.
(2) Load-Reserved (LR) and Store-Conditional (SC)
Addresses locked by LR instructions are tracked in a stack data structure. LR instruction pushes its target address to the stack, and SC instruction pops the top address from the stack. As specified by RISC-V ISA, a SC fails if its target address does not match with the most recent LR.
Previously, there was a single stack for all hardware thread contexts. A shared stack between thread contexts can lead to a infinite sequence of failed SCs if LRs from other threads keep pushing new addresses to this stack.
This patch gives each context its private stack to address the problem.
This patch also adds extra memory fence micro-ops to lr/sc to guarantee a correct execution order of memory instructions with respect to release consistency model.
Change-Id: I1e95900367c89dd866ba872a5203f63359ac51ae Reviewed-on: https://gem5-review.googlesource.com/c/8189 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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13633:985e9c018cbf |
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02-Apr-2018 |
Tuan Ta <qtt2@cornell.edu> |
riscv: remove NonSpeculative flag from fence inst
Fence instruction origially had two flags NonSpeculative and MemBarrier. In O3 model, MemBarrier instructions are inserted into the instruction queue by the InstructionQueue::insertBarrier (at src/cpu/o3/iew_impl.hh:1083). Barrier instructions are implicitly assumed to be non-speculative.
Adding NonSpeculative flag to fence instruction makes it inserted into the instruction queue twice (at src/cpu/o3/iew_impl.hh:1083 and :1111). This can lead to a deadlock if both pointers to the instruction are not cleared from the queue when the instruction retires.
This patch removes NonSpeculative flag from the fence inst.
Change-Id: I26573d12a0b52f43b73c0e51158286dc98d05ea4 Reviewed-on: https://gem5-review.googlesource.com/c/8183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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13612:12ae022f3a30 |
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19-Nov-2018 |
Gabe Black <gabeblack@google.com> |
riscv: Get rid of some ISA specific register types.
Change-Id: Ie812cf1d42536094273ba2ec731c16cca38db100 Reviewed-on: https://gem5-review.googlesource.com/c/14466 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
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12850:7036cad54910 |
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10-Jun-2018 |
Alec Roelke <alec.roelke@gmail.com> |
arch-riscv: Add xret instructions
This patch adds the uret, sret, and mret instructions for use with returning from user-, supervisor-, and machine-level code, respectively. These instructions read the STATUS register to determine the previous privilege level and modify it to re-enable interrupts at the old privilege level. These instructions can only be executed at the corresponding privilege level or higher.
Change-Id: I6125c31cb2fdcc3f83eca86910519e81ffbbbfc9 Reviewed-on: https://gem5-review.googlesource.com/11136 Maintainer: Alec Roelke <alec.roelke@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Robert Scheffel <robert.scheffel1@tu-dresden.de>
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12849:7f43ad13ebf0 |
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18-Feb-2018 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Add support for trap value register
RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses.
Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
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12807:0baf4adc1a45 |
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07-Jul-2018 |
Austin Harris <austinharris@utexas.edu> |
arch-riscv: Fix the srlw and srliw instructions.
Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/11669 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
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12695:3df197da6069 |
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10-Dec-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Update CSR implementations
This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters.
Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch.
Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12596:5102ba06fca5 |
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01-Mar-2018 |
Tuan Ta <qtt2@cornell.edu> |
riscv: throw IllegalInstFault when decoding invalid instructions
If an instruction is invalid, some assertions may in the decoder may fail the entire simulation. Instead, we want to raise an IllegalInstFault instead of failing immediately in the decoder if the invalid instruction is being speculatively executed.
Change-Id: I5cb72ba06f07f173922f86897ddfdf677e8c702f Reviewed-on: https://gem5-review.googlesource.com/9261 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Monir Zaman <monir.zaman.m@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12535:22fe7cd9a852 |
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19-Feb-2018 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Fix compressed branch op offset
There is a bug in RISC-V's compressed branch instructions where the offsets are not stored in ImmOp's immediate field, causing incorrect branchTarget() return values. This patch adds a new compressed branch op format, CBOp, which correctly stores the offset.
Change-Id: Iac6e9b091d63f3dce4717ee5a9ec31a7cbd6c377 Reviewed-on: https://gem5-review.googlesource.com/8441 Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12445:cda4ad06d1ff |
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08-Dec-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Fix floating-poing op classes
This patch applies correct miscellaneous or multiply-accumulate op classes to floating point instructions which had previously been incorrectly classed as add or multiply instructions.
Change-Id: I959dd8d3152aa341e0f060b003ce1da8c4d688fb Reviewed-on: https://gem5-review.googlesource.com/6521 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12444:06e9f1927cc7 |
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04-Dec-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Fix floating-point conversion bugs
Using the fetestexcept function to check for specific types of floating point exceptions is unreliable for some kinds of floating-point-to-integer conversion operations. RISC-V code used to make use of them to check for some exceptional cases like overflow and underflow, which caused incorrect output when compiler optimization is turned on. This patch changes the use of fetestexcept to explicit checks for those exceptional cases.
Change-Id: Id983906ea0664dc246e115a9e470d9ab7733bde1 Reviewed-on: https://gem5-review.googlesource.com/6402 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12428:ddc6b7179c81 |
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02-Dec-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Make use of ImmOp's polymorphism
This patch makes use of ImmOp's polymorphism to remove unnecessary casting from the implementations of arithmetic instructions with immediate operands and to remove the CUIOp format by combining it with the CIOp format (compressed arithmetic instructions with immediate operands). Interestingly, RISC-V specifies that instructions with unsigned immediate operands still need to sign-extend the immediates from 12 (or 20) bits to 64 bits, so that is left alone.
Change-Id: If20d70c1e90f379b9ed8a4155b2b9222b6defe16 Reviewed-on: https://gem5-review.googlesource.com/6401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tuan Ta <qtt2@cornell.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12322:e5a1d42b876b |
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07-Nov-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Move parts of mem insts out of ISA
This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class.
Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12138:5f06b9aa2fde |
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14-Jul-2017 |
Gabe Black <gabeblack@google.com> |
riscv: Disambiguate between the C and C++ versions of isnan and isinf.
When both the C and C++ versions are visible, the compiler will complain that it doesn't know which one to use. By specifying the std namespace, it will know to use the C++ version.
Change-Id: Ie1bbe1d95eadbad9644b4915c21f924d7d5c0b22 Reviewed-on: https://gem5-review.googlesource.com/4060 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12136:1070125670e2 |
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13-Jul-2017 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: Fix bugs with RISC-V decoder and detailed CPUs
This patch fixes some bugs that were missed with the changes to the decoder that enabled compatibility with compressed instructions. In order to accommodate speculation with variable instruction widths, a few assertions in decoder had to be changed to returning faults as the specification describes should normally happen. The rest of these assertions will be changed in a later patch.
[Remove commented-out debugging line and add clarifying comment to registerName in utility.hh.]
Change-Id: I3f333008430d4a905cb59547a3513f5149b43b95 Reviewed-on: https://gem5-review.googlesource.com/4041 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12120:133620bfc43b |
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14-Jun-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Add support for compressed extension RV64C
This patch adds compatibility with the 64-bit compressed extension to the RISC-V ISA, RV64C. Current versions of the toolchain may use compressed instructions in glibc by default, which can only be overridden by recompiling the entire toolchain (simply adding "-march=rv64g" or "-march=rv64imafd" when compiling a binary is not sufficient to use uncompressed instructions in glibc functions in the binary).
[Update diassembly generation for new RegId type.] [Rebase onto master.]
Change-Id: Ifd5a5ea746704ce7e1b111442c3eb84c509a98b4 Reviewed-on: https://gem5-review.googlesource.com/3860 Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Alec Roelke <ar4jc@virginia.edu>
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12119:e9ef3ee3171d |
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15-Jun-2017 |
Alec Roelke <ar4jc@virginia.edu> |
arch-riscv: Restructure ISA description
This patch restructures the RISC-V ISA description to use fewer classes and improve its ability to be extended with nonstandard extensions in the future. It also cleans up the disassembly for some of the CSR and system instructions by removing source and destination registers for instructions that don't have any.
[Fix class UImmOp to have an "imm" member rather than "uimm".] [Update disassembly generation for new RegId class.]
Change-Id: Iec1c782020126e5e8e73460b84e31c7b5a5971d9 Reviewed-on: https://gem5-review.googlesource.com/3800 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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11965:41e942451f59 |
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21-Mar-2017 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: fix Linux problems with LR and SC ops
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions.
Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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11729:f37b5fcd66fe |
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30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: [Patch 7/5] Corrected LRSC semantics
RISC-V makes use of load-reserved and store-conditional instructions to enable creation of lock-free concurrent data manipulation as well as ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO instructions (the latter of which do not follow LR/SC semantics). This patch is a correction to patch 4, which added these instructions to the implementation of RISC-V. It modifies locked_mem.hh and the implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5 flags and return the proper values.
An important difference between gem5's LLSC semantics and RISC-V's LR/SC ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V uses 0 to indicate success and nonzero to indicate failure where the value would indicate the error, but currently only 1 is reserved as a failure code by the ISA reference.
This is the seventh patch in the series which originally consisted of five patches that added the RISC-V ISA to gem5. The original five patches added all of the instructions and added support for more detailed CPU models and the sixth patch corrected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions.
[Removed some commented-out code from locked_mem.hh.] Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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11726:11950d45640b |
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30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: [Patch 4/5] Added RISC-V atomic memory extension RV64A
Fourth of five patches adding RISC-V to GEM5. This patch adds the RV64A extension, which includes atomic memory instructions. These instructions atomically read a value from memory, modify it with a value contained in a source register, and store the original memory value in the destination register and modified value back into memory. Because this requires two memory accesses and GEM5 does not support two timing memory accesses in a single instruction, each of these instructions is split into two micro- ops: A "load" micro-op, which reads the memory, and a "store" micro-op, which modifies and writes it back. Each atomic memory instruction also has two bits that acquire and release a lock on its memory location. Additionally, there are atomic load and store instructions that only either load or store, but not both, and can acquire or release memory locks.
Note that because the current implementation of RISC-V only supports one core and one thread, it doesn't make sense to make use of AMO instructions. However, they do form a standard extension of the RISC-V ISA, so they are included mostly as a placeholder for when multithreaded execution is implemented. As a result, any tests for their correctness in a future patch may be abbreviated.
Patch 1 introduced RISC-V and implemented the base instruction set, RV64I; patch 2 implemented the integer multiply extension, RV64M; and patch 3 implemented the single- and double-precision floating point extensions, RV64FD.
Patch 5 will add support for timing, minor, and detailed CPU models that isn't present in patches 1-4.
[Added missing file amo.isa] [Replaced information removed from initial patch that was missed during division into multiple patches.] [Fixed some minor formatting issues.] [Fixed oversight where LR and SC didn't have both AQ and RL flags.] Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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11725:eb58f1bbeac8 |
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30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD
Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions.
Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M.
Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches.
[Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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11724:d92c26d481b7 |
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30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
riscv: [Patch 2/5] Added RISC-V multiply extension RV64M
Second of five patches adding RISC-V to GEM5. This patch adds the RV64M extension, which includes integer multiply and divide instructions.
Patch 1 introduced RISC-V and implemented the base instruction set, RV64I.
Patch 3 will implement the floating point extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A; and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches.
[Added mulw instruction that was missed when dividing changes among patches.] Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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11723:0596db108c53 |
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30-Nov-2016 |
Alec Roelke <ar4jc@virginia.edu> |
arch: [Patch 1/5] Added RISC-V base instruction set RV64I
First of five patches adding RISC-V to GEM5. This patch introduces the base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall emulation. The multiply, floating point, and atomic memory instructions will be added in additional patches, as well as support for more detailed CPU models. The loader is also modified to be able to parse RISC-V ELF files, and a "Hello world\!" example for RISC-V is added to test-progs.
Patch 2 will implement the multiply extension, RV64M; patch 3 will implement the floating point (single- and double-precision) extensions, RV64FD; patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches (such as handling locked memory).
[Removed several unused parameters and imports from RiscvInterrupts.py, RiscvISA.py, and RiscvSystem.py.] [Fixed copyright information in RISC-V files copied from elsewhere that had ARM licenses attached.] [Reorganized instruction definitions in decoder.isa so that they are sorted by opcode in preparation for the addition of ISA extensions M, A, F, D.] [Fixed formatting of several files, removed some variables and instructions that were missed when moving them to other patches, fixed RISC-V Foundation copyright attribution, and fixed history of files copied from other architectures using hg copy.] [Fixed indentation of switch cases in isa.cc.] [Reorganized syscall descriptions in linux/process.cc to remove large number of repeated unimplemented system calls and added implmementations to functions that have received them since it process.cc was first created.] [Fixed spacing for some copyright attributions.] [Replaced the rest of the file copies using hg copy.] [Fixed style check errors and corrected unaligned memory accesses.] [Fix some minor formatting mistakes.] Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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