| /gem5/src/mem/ruby/common/ |
| H A D | Consumer.cc | 36 scheduleEventAbsolute(em->clockEdge(timeDelta));
51 Tick t = em->clockEdge();
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| /gem5/src/mem/ruby/system/ |
| H A D | VIPERCoalescer.cc | 218 clockEdge(), addr, (uint8_t*) 0, 0, 0,
225 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
249 clockEdge(), addr, (uint8_t*) 0, 0, 0,
256 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
277 clockEdge(), addr, (uint8_t*) 0, 0, 0,
284 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
293 clockEdge(), addr, (uint8_t*) 0, 0, 0,
300 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
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| H A D | DMASequencer.cc | 96 std::make_shared<SequencerMsg>(clockEdge());
114 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
141 std::make_shared<SequencerMsg>(clockEdge());
164 m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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| H A D | Sequencer.cc | 127 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
170 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
637 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
654 m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
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| /gem5/src/cpu/testers/memtest/ |
| H A D | memtest.cc | 122 schedule(noRequestEvent, clockEdge(progressCheck));
194 reschedule(noResponseEvent, clockEdge(progressCheck));
301 schedule(tickEvent, clockEdge(interval));
305 reschedule(noRequestEvent, clockEdge(progressCheck), true);
312 schedule(noResponseEvent, clockEdge(progressCheck));
336 schedule(tickEvent, clockEdge(interval));
337 reschedule(noRequestEvent, clockEdge(progressCheck), true);
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| /gem5/src/mem/ |
| H A D | hmc_controller.cc | 80 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
99 clockEdge(Cycles(1)));
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| H A D | bridge.cc | 139 slavePort.schedTimingResp(pkt, bridge.clockEdge(delay) +
193 masterPort.schedTimingReq(pkt, bridge.clockEdge(delay) +
270 bridge.clockEdge()));
311 bridge.clockEdge()));
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| H A D | serial_link.cc | 152 Tick t = serial_link.clockEdge(cycles);
213 Tick t = serial_link.clockEdge(cycles);
300 Tick t = serial_link.clockEdge(cycles);
345 Tick t = serial_link.clockEdge(cycles);
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| H A D | noncoherent_xbar.cc | 139 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
158 clockEdge(Cycles(1)));
215 Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
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| /gem5/src/sim/ |
| H A D | clocked_object.hh | 180 clockEdge(Cycles cycles=Cycles(0)) const function in class:Clocked
216 Tick nextCycle() const { return clockEdge(Cycles(1)); }
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| H A D | ticked_object.cc | 65 object.schedule(event, object.clockEdge(Cycles(1)));
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| H A D | ticked_object.hh | 109 object.schedule(event, object.clockEdge(Cycles(1)));
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | AbstractController.cc | 137 reanalyzeMessages(addr, clockEdge());
158 reanalyzeMessages(addr, clockEdge());
188 (*vec_iter)->reanalyzeAllMessages(clockEdge());
260 memoryPort.schedTimingReq(pkt, clockEdge(latency));
285 memoryPort.schedTimingReq(pkt, clockEdge(latency));
303 memoryPort.schedTimingReq(pkt, clockEdge(latency));
333 std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
355 getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
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| /gem5/src/dev/ |
| H A D | pixelpump.cc | 158 schedule(evBeginLine, clockEdge());
198 schedule(evHSyncBegin, clockEdge(h_sync_begin));
201 schedule(evHSyncEnd, clockEdge(h_sync_end));
208 schedule(evRenderPixels, clockEdge(h_first_visible));
211 schedule(evBeginLine, clockEdge(_timings.cyclesPerLine()));
244 schedule(evRenderPixels, clockEdge(Cycles(pxl_count)));
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| /gem5/src/mem/ruby/network/garnet2.0/ |
| H A D | NetworkLink.cc | 72 link_consumer->scheduleEventAbsolute(clockEdge(m_latency));
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| H A D | OutputUnit.hh | 94 m_out_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1)));
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| H A D | NetworkInterface.cc | 139 scheduleEventAbsolute(clockEdge(Cycles(1)));
185 Tick curTime = clockEdge();
269 outCreditLink->scheduleEventAbsolute(clockEdge(Cycles(1)));
284 Tick curTime = clockEdge();
478 outNetLink->scheduleEventAbsolute(clockEdge(Cycles(1)));
512 while (it->isReady(clockEdge())) { // Is there a message waiting
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| H A D | InputUnit.cc | 149 m_credit_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1)));
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| /gem5/src/arch/sparc/ |
| H A D | ua2005.cc | 118 cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
134 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
205 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
346 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
374 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
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| /gem5/src/mem/cache/prefetch/ |
| H A D | access_map_pattern_matching.cc | 65 schedule(epochEvent, clockEdge(epochCycles));
71 schedule(epochEvent, clockEdge(epochCycles));
81 clockEdge(epochCycles);
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| /gem5/src/cpu/simple/ |
| H A D | timing.cc | 114 schedule(fetchEvent, clockEdge());
221 schedule(fetchEvent, clockEdge(Cycles(0)));
273 new IprEvent(pkt, this, clockEdge(delay));
483 new IprEvent(dcache_pkt, this, clockEdge(delay));
750 clockEdge(syscallRetryLatency) : clockEdge();
858 tickEvent.schedule(pkt, cpu->clockEdge());
985 tickEvent.schedule(pkt, cpu->clockEdge());
992 cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
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| /gem5/src/mem/ruby/network/simple/ |
| H A D | Throttle.cc | 100 Tick current_time = m_switch->clockEdge();
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| /gem5/src/dev/arm/ |
| H A D | pl111.cc | 467 schedule(intEvent, clockEdge());
518 schedule(intEvent, clockEdge());
542 schedule(readEvent, clockEdge(ticksToCycles(startTime -
551 schedule(fillFifoEvent, clockEdge());
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| H A D | smmu_v3_proc.cc | 129 scheduleWakeup(smmu.clockEdge(cycles));
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| /gem5/src/mem/cache/ |
| H A D | cache.cc | 297 Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
773 completion_time += clockEdge(responseLatency) +
789 completion_time += clockEdge(responseLatency) +
807 completion_time += clockEdge(responseLatency) +
962 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1056 Tick forward_time = clockEdge(forwardLatency) +
|