1/*
2 * Copyright (c) 2008 Princeton University
3 * Copyright (c) 2016 Georgia Institute of Technology
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Niket Agarwal
30 *          Tushar Krishna
31 */
32
33
34#include "mem/ruby/network/garnet2.0/InputUnit.hh"
35
36#include "base/stl_helpers.hh"
37#include "debug/RubyNetwork.hh"
38#include "mem/ruby/network/garnet2.0/Credit.hh"
39#include "mem/ruby/network/garnet2.0/Router.hh"
40
41using namespace std;
42using m5::stl_helpers::deletePointers;
43
44InputUnit::InputUnit(int id, PortDirection direction, Router *router)
45            : Consumer(router)
46{
47    m_id = id;
48    m_direction = direction;
49    m_router = router;
50    m_num_vcs = m_router->get_num_vcs();
51    m_vc_per_vnet = m_router->get_vc_per_vnet();
52
53    m_num_buffer_reads.resize(m_num_vcs/m_vc_per_vnet);
54    m_num_buffer_writes.resize(m_num_vcs/m_vc_per_vnet);
55    for (int i = 0; i < m_num_buffer_reads.size(); i++) {
56        m_num_buffer_reads[i] = 0;
57        m_num_buffer_writes[i] = 0;
58    }
59
60    creditQueue = new flitBuffer();
61    // Instantiating the virtual channels
62    m_vcs.resize(m_num_vcs);
63    for (int i=0; i < m_num_vcs; i++) {
64        m_vcs[i] = new VirtualChannel(i);
65    }
66}
67
68InputUnit::~InputUnit()
69{
70    delete creditQueue;
71    deletePointers(m_vcs);
72}
73
74/*
75 * The InputUnit wakeup function reads the input flit from its input link.
76 * Each flit arrives with an input VC.
77 * For HEAD/HEAD_TAIL flits, performs route computation,
78 * and updates route in the input VC.
79 * The flit is buffered for (m_latency - 1) cycles in the input VC
80 * and marked as valid for SwitchAllocation starting that cycle.
81 *
82 */
83
84void
85InputUnit::wakeup()
86{
87    flit *t_flit;
88    if (m_in_link->isReady(m_router->curCycle())) {
89
90        t_flit = m_in_link->consumeLink();
91        int vc = t_flit->get_vc();
92        t_flit->increment_hops(); // for stats
93
94        if ((t_flit->get_type() == HEAD_) ||
95            (t_flit->get_type() == HEAD_TAIL_)) {
96
97            assert(m_vcs[vc]->get_state() == IDLE_);
98            set_vc_active(vc, m_router->curCycle());
99
100            // Route computation for this vc
101            int outport = m_router->route_compute(t_flit->get_route(),
102                m_id, m_direction);
103
104            // Update output port in VC
105            // All flits in this packet will use this output port
106            // The output port field in the flit is updated after it wins SA
107            grant_outport(vc, outport);
108
109        } else {
110            assert(m_vcs[vc]->get_state() == ACTIVE_);
111        }
112
113
114        // Buffer the flit
115        m_vcs[vc]->insertFlit(t_flit);
116
117        int vnet = vc/m_vc_per_vnet;
118        // number of writes same as reads
119        // any flit that is written will be read only once
120        m_num_buffer_writes[vnet]++;
121        m_num_buffer_reads[vnet]++;
122
123        Cycles pipe_stages = m_router->get_pipe_stages();
124        if (pipe_stages == 1) {
125            // 1-cycle router
126            // Flit goes for SA directly
127            t_flit->advance_stage(SA_, m_router->curCycle());
128        } else {
129            assert(pipe_stages > 1);
130            // Router delay is modeled by making flit wait in buffer for
131            // (pipe_stages cycles - 1) cycles before going for SA
132
133            Cycles wait_time = pipe_stages - Cycles(1);
134            t_flit->advance_stage(SA_, m_router->curCycle() + wait_time);
135
136            // Wakeup the router in that cycle to perform SA
137            m_router->schedule_wakeup(Cycles(wait_time));
138        }
139    }
140}
141
142// Send a credit back to upstream router for this VC.
143// Called by SwitchAllocator when the flit in this VC wins the Switch.
144void
145InputUnit::increment_credit(int in_vc, bool free_signal, Cycles curTime)
146{
147    Credit *t_credit = new Credit(in_vc, free_signal, curTime);
148    creditQueue->insert(t_credit);
149    m_credit_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1)));
150}
151
152
153uint32_t
154InputUnit::functionalWrite(Packet *pkt)
155{
156    uint32_t num_functional_writes = 0;
157    for (int i=0; i < m_num_vcs; i++) {
158        num_functional_writes += m_vcs[i]->functionalWrite(pkt);
159    }
160
161    return num_functional_writes;
162}
163
164void
165InputUnit::resetStats()
166{
167    for (int j = 0; j < m_num_buffer_reads.size(); j++) {
168        m_num_buffer_reads[j] = 0;
169        m_num_buffer_writes[j] = 0;
170    }
171}
172