/gem5/util/plot_dram/ |
H A D | dram_lat_mem_rd_plot.py | 72 # Get the address ranges 74 ranges = [] 80 ranges.append(int(line) / 1024) 82 match = re.match("lat_mem_rd with (\d+) iterations, ranges:.*", line) 90 print "Failed to get address ranges, ensure simout is up-to-date" 120 if not (len(ranges) == len(final_rd_lat)): 121 print "Address ranges (%d) and read latency (%d) do not match" % \ 122 (len(ranges), len(final_rd_lat)) 125 for (r, l) in zip(ranges, final_rd_lat): 132 plt.semilogx(ranges, final_rd_la [all...] |
/gem5/src/dev/ |
H A D | io_device.cc | 84 AddrRangeList ranges; local 86 ranges.push_back(RangeSize(pioAddr, pioSize)); 87 return ranges;
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/gem5/src/mem/ |
H A D | Bridge.py | 53 ranges = VectorParam.AddrRange([AllMemory], variable in class:Bridge 54 "Address ranges to pass through the bridge")
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H A D | SerialLink.py | 58 ranges = VectorParam.AddrRange([AllMemory], variable in class:SerialLink 59 "Address ranges to pass through the serial_link")
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H A D | simple_mem.cc | 273 AddrRangeList ranges; local 274 ranges.push_back(memory.getAddrRange()); 275 return ranges;
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H A D | physical.cc | 131 // if we already got interleaved ranges that are not 165 // if there is still interleaved ranges waiting to be merged, go 246 AddrRangeList ranges; local 252 // if we already got interleaved ranges that are not 257 ranges.push_back(AddrRange(intlv_ranges)); 263 ranges.push_back(r.first); 268 // if there is still interleaved ranges waiting to be merged, 271 ranges.push_back(AddrRange(intlv_ranges)); 274 return ranges;
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H A D | addr_mapper.cc | 243 // Simply return the original ranges as given by the parameters 244 AddrRangeList ranges(originalRanges.begin(), originalRanges.end()); 245 return ranges;
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H A D | bridge.hh | 65 * it and responds to a fixed set of address ranges. 99 * responses. The slave port has a set of address ranges that it 119 /** Address ranges to pass through the bridge */ 120 const AddrRangeList ranges; member in class:Bridge::BridgeSlavePort 172 * @param _ranges a number of address ranges to forward
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H A D | serial_link.hh | 95 * responses. The slave port has a set of address ranges that it 115 /** Address ranges to pass through the serial_link */ 116 const AddrRangeList ranges; member in class:SerialLink::SerialLinkSlavePort 163 * @param _ranges a number of address ranges to forward
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H A D | bridge.cc | 63 delay(_delay), ranges(_ranges.begin(), _ranges.end()), 82 ticksToCycles(p->delay), p->resp_size, p->ranges), 107 // notify the master side of our address ranges 393 return ranges;
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H A D | dramsim2.cc | 365 AddrRangeList ranges; local 366 ranges.push_back(memory.getAddrRange()); 367 return ranges;
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/gem5/src/mem/ruby/network/ |
H A D | Network.cc | 89 const AddrRangeList &ranges = abs_cntrl->getAddrRanges(); local 90 if (!ranges.empty()) { 94 .ranges = ranges 206 auto &ranges = node.ranges; local 207 for (AddrRange &range: ranges) {
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/gem5/src/base/ |
H A D | addr_range.hh | 59 * number of tests to check if two ranges intersect, if a range 61 * AddrRange also support interleaved ranges, to stripe across cache 70 * ranges to a contiguous range. 204 * ranges. 206 * @param ranges Interleaved ranges to be merged 208 AddrRange(const std::vector<AddrRange>& ranges) argument 211 if (!ranges.empty()) { 213 _start = ranges.front()._start; 214 _end = ranges [all...] |
/gem5/src/dev/arm/ |
H A D | gic_v2m.cc | 84 // Assert SPI ranges start at 32 99 AddrRangeList ranges; local 101 ranges.push_back(RangeSize(frames[i]->addr, FRAME_SIZE)); 103 return ranges;
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/gem5/ext/sst/ |
H A D | ExtMaster.cc | 93 ranges.insert(range); 224 if (ranges.find(range) == ranges.end()) { // i.e. if not found, 231 ranges.insert(range);
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H A D | ExtMaster.hh | 94 std::set<AddrRange> ranges; member in class:SST::gem5::ExtMaster
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/gem5/configs/dram/ |
H A D | lat_mem_rd.py | 154 ranges = [min_range] variable 157 while ranges[-1] < max_range: 158 new_range = ranges[-1] + step 161 ranges.append(new_range) 221 for r in ranges: 310 print("lat_mem_rd with %d iterations, ranges:" % iterations) 311 for r in ranges:
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/gem5/configs/common/ |
H A D | HMC.py | 314 # create memory ranges for the serial links 316 # Memmory ranges of serial link for arch-0. Same as the ranges of vault 321 # Memmory ranges of serial link for arch-1. Distributed range accross 326 # Memmory ranges of serial link for arch-2 'Mixed' address distribution 336 # ranges w.r.t to architecture 337 sl = [SerialLink(ranges=ser_ranges[i], 394 # create memory ranges for the vault controllers 451 # Change the default values for ranges of bridge 452 system.hmc_dev.buffers[index].ranges [all...] |
/gem5/tests/configs/ |
H A D | twosys-tsunami-simple-atomic.py | 64 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 96 drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
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/gem5/src/mem/ruby/system/ |
H A D | RubyPort.hh | 97 { AddrRangeList ranges; return ranges; } local
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/gem5/src/dev/x86/ |
H A D | i8042.cc | 80 AddrRangeList ranges; local 82 ranges.push_back(RangeSize(dataPort, 1)); 83 ranges.push_back(RangeSize(commandPort, 1)); 84 return ranges;
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/gem5/src/dev/serial/ |
H A D | uart8250.cc | 281 AddrRangeList ranges; local 282 ranges.push_back(RangeSize(pioAddr, pioSize)); 283 return ranges;
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/gem5/src/gpu-compute/ |
H A D | lds_state.hh | 189 AddrRangeList ranges; local 190 ranges.push_back(ownerLds->getAddrRange()); 191 return ranges;
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/gem5/configs/ruby/ |
H A D | MOESI_CMP_directory.py | 142 # Create the L2s interleaved addr ranges 149 ranges = [] 155 ranges.append(addr_range) 156 l2_addr_ranges.append(ranges)
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/gem5/src/mem/qos/ |
H A D | mem_sink.cc | 353 AddrRangeList ranges; local 354 ranges.push_back(memory.getAddrRange()); 355 return ranges;
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